[PATCH] D76773: [PowerPC] Fix PR45297

[Kai Luo via Phabricator via llvm-commits]

lkail created this revision.
lkail added reviewers: PowerPC, nemanjai, steven.zhang.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
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lkail edited the summary of this revision.
Herald added a subscriber: wuzish.

In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the `PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch should resolve PR45297.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76773

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pr45297.ll


Index: llvm/test/CodeGen/PowerPC/pr45297.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr45297.ll
+++ llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,8 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mattr=+altivec -mattr=-power8-vector -mattr=-vsx < %s | FileCheck %s
-; XFAIL: *
 
 define dso_local void @test(float %0) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fctiwz 0, 1
+; CHECK-NEXT:    addi 3, 1, -4
+; CHECK-NEXT:    stfiwx 0, 0, 3
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    stw 3, 0(3)
+; CHECK-NEXT:    blr
 entry:
   %1 = fptosi float %0 to i32
   store i32 %1, i32* undef, align 4
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13694,7 +13694,7 @@
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
-  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
+  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
     return SDValue();
 


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