[PATCH] D76740: [ARM] MVE VMULL patterns

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12166
+      return SDValue();
+    if (isAllOnesConstant(Mask->getOperand(0)) &&
+        isNullConstant(Mask->getOperand(1)) &&
----------------
I'm a bit confused here... this looks like the AND mask is taking the 'top' parts of the elements, and if so, why don't we have to handle a 'bottom' element mask? Is this to do  with the revs I see in the isel patterns?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76740/new/

https://reviews.llvm.org/D76740