[PATCH] D76767: [RISCV] Support negative constants in CompressInstEmitter

[Simon Cook via Phabricator via llvm-commits]

simoncook created this revision.
simoncook added reviewers: asb, lenary, PaoloS.
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Some compressed instructions match against negative values which in
TableGen are represented as unsigned numbers, but when creating
MCInst/MachineInstr these need to be signed numbers. Expliclty
convert these such that these patterns will now match the intended
instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76767

Files:
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp


Index: llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -730,7 +730,8 @@
             << "(MI.getOperand(" + std::to_string(OpNo) + ").isImm()) &&\n" +
                    "      (MI.getOperand(" + std::to_string(OpNo) +
                    ").getImm() == " +
-                   std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
+                   std::to_string((int64_t)SourceOperandMap[OpNo].Data.Imm) +
+                   ") &&\n";
         break;
       case OpData::Reg: {
         Record *Reg = SourceOperandMap[OpNo].Data.Reg;
@@ -799,20 +800,21 @@
             DestOperand.Rec, StringRef("MCOperandPredicate"));
           CondStream.indent(6)
               << Namespace + "ValidateMCOperand(" + "MCOperand::createImm(" +
-                     std::to_string(DestOperandMap[OpNo].Data.Imm) + "), STI, " +
-                     std::to_string(Entry) + ") &&\n";
+                     std::to_string((int64_t)DestOperandMap[OpNo].Data.Imm) +
+                     "), STI, " + std::to_string(Entry) + ") &&\n";
         } else {
           unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
             DestOperand.Rec, StringRef("ImmediateCode"));
           CondStream.indent(6)
               << Namespace + "ValidateMachineOperand(" + "MachineOperand::CreateImm(" +
-                     std::to_string(DestOperandMap[OpNo].Data.Imm) + "), SubTarget, " +
-                     std::to_string(Entry) + ") &&\n";
+                     std::to_string((int64_t)DestOperandMap[OpNo].Data.Imm) +
+                     "), SubTarget, " + std::to_string(Entry) + ") &&\n";
         }
         if (CompressOrUncompress)
           CodeStream.indent(6)
               << "OutInst.addOperand(MCOperand::createImm(" +
-                     std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
+                     std::to_string((int64_t)DestOperandMap[OpNo].Data.Imm) +
+                     "));\n";
       } break;
       case OpData::Reg: {
         if (CompressOrUncompress) {


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