[llvm] e872502 - [ARM][MVE] Add HorizontalReduction flag
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 25 04:27:18 PDT 2020
Author: Sam Parker
Date: 2020-03-25T11:12:03Z
New Revision: e87250202d15ef36a78247ac42685204258314a9
URL: https://github.com/llvm/llvm-project/commit/e87250202d15ef36a78247ac42685204258314a9
DIFF: https://github.com/llvm/llvm-project/commit/e87250202d15ef36a78247ac42685204258314a9.diff
LOG: [ARM][MVE] Add HorizontalReduction flag
Add a target flag for instructions that reduce into one, or more,
scalar reg(s), including variants of:
- VADDV
- VABAV
- VMINV/VMAXV
- VMLADAV
Differential Revision: https://reviews.llvm.org/D76683
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrFormats.td
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
llvm/unittests/Target/ARM/MachineInstrTest.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 535784bc3ce3..39646e3d3557 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -409,6 +409,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
bit validForTailPredication = 0;
bit retainsPreviousHalfElement = 0;
+ bit horizontalReduction = 0;
// If this is a pseudo instruction, mark it isCodeGenOnly.
let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
@@ -423,6 +424,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
let TSFlags{19} = thumbArithFlagSetting;
let TSFlags{20} = validForTailPredication;
let TSFlags{21} = retainsPreviousHalfElement;
+ let TSFlags{22} = horizontalReduction;
let Constraints = cstr;
let Itinerary = itin;
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index e9e037df66f4..fcd3b5775869 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -556,6 +556,7 @@ class MVE_VABAV<string suffix, bit U, bits<2> size>
let Inst{5} = Qm{3};
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b1;
+ let horizontalReduction = 1;
}
multiclass MVE_VABAV_m<MVEVectorVTInfo VTI> {
@@ -605,6 +606,7 @@ class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
let Inst{5} = A;
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0;
+ let horizontalReduction = 1;
}
def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
@@ -678,6 +680,7 @@ class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
let Inst{5} = A;
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0;
+ let horizontalReduction = 1;
}
def SDTVecReduceL : SDTypeProfile<2, 1, [ // VADDLV
@@ -749,6 +752,7 @@ class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
let Inst{6-5} = 0b00;
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0;
+ let horizontalReduction = 1;
let Predicates = [HasMVEFloat];
}
@@ -808,6 +812,7 @@ class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
let Inst{6-5} = 0b00;
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0;
+ let horizontalReduction = 1;
}
multiclass MVE_VMINMAXV_p<string iname, bit notAbs, bit isMin,
@@ -899,6 +904,7 @@ class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
let Inst{5} = A;
let Inst{3-1} = Qm{2-0};
let Inst{0} = bit_0;
+ let horizontalReduction = 1;
}
multiclass MVE_VMLAMLSDAV_A<string iname, string x, MVEVectorVTInfo VTI,
@@ -1057,6 +1063,7 @@ class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
let Inst{5} = A;
let Inst{3-1} = Qm{2-0};
let Inst{0} = bit_0;
+ let horizontalReduction = 1;
}
multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
index 0c9925cf1d9e..7d7d0af23893 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
@@ -400,6 +400,9 @@ namespace ARMII {
// and leaves the other half untouched.
RetainsPreviousHalfElement = 1 << 21,
+ // Whether the instruction produces a scalar result from vector operands.
+ HorizontalReduction = 1 << 22,
+
//===------------------------------------------------------------------===//
// Code domain.
DomainShift = 15,
diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 609785818900..90f84d4e5aa1 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -10,6 +10,163 @@
using namespace llvm;
+TEST(MachineInstructionHorizontalReduction, IsCorrect) {
+ using namespace ARM;
+
+ auto HorizontalReduction = [](unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ break;
+ case MVE_VABAVs16:
+ case MVE_VABAVs32:
+ case MVE_VABAVs8:
+ case MVE_VABAVu16:
+ case MVE_VABAVu32:
+ case MVE_VABAVu8:
+ case MVE_VADDLVs32acc:
+ case MVE_VADDLVs32no_acc:
+ case MVE_VADDLVu32acc:
+ case MVE_VADDLVu32no_acc:
+ case MVE_VADDVs16acc:
+ case MVE_VADDVs16no_acc:
+ case MVE_VADDVs32acc:
+ case MVE_VADDVs32no_acc:
+ case MVE_VADDVs8acc:
+ case MVE_VADDVs8no_acc:
+ case MVE_VADDVu16acc:
+ case MVE_VADDVu16no_acc:
+ case MVE_VADDVu32acc:
+ case MVE_VADDVu32no_acc:
+ case MVE_VADDVu8acc:
+ case MVE_VADDVu8no_acc:
+ case MVE_VMAXAVs16:
+ case MVE_VMAXAVs32:
+ case MVE_VMAXAVs8:
+ case MVE_VMAXNMAVf16:
+ case MVE_VMAXNMAVf32:
+ case MVE_VMAXNMVf16:
+ case MVE_VMAXNMVf32:
+ case MVE_VMAXVs16:
+ case MVE_VMAXVs32:
+ case MVE_VMAXVs8:
+ case MVE_VMAXVu16:
+ case MVE_VMAXVu32:
+ case MVE_VMAXVu8:
+ case MVE_VMINAVs16:
+ case MVE_VMINAVs32:
+ case MVE_VMINAVs8:
+ case MVE_VMINNMAVf16:
+ case MVE_VMINNMAVf32:
+ case MVE_VMINNMVf16:
+ case MVE_VMINNMVf32:
+ case MVE_VMINVs16:
+ case MVE_VMINVs32:
+ case MVE_VMINVs8:
+ case MVE_VMINVu16:
+ case MVE_VMINVu32:
+ case MVE_VMINVu8:
+ case MVE_VMLADAVas16:
+ case MVE_VMLADAVas32:
+ case MVE_VMLADAVas8:
+ case MVE_VMLADAVau16:
+ case MVE_VMLADAVau32:
+ case MVE_VMLADAVau8:
+ case MVE_VMLADAVaxs16:
+ case MVE_VMLADAVaxs32:
+ case MVE_VMLADAVaxs8:
+ case MVE_VMLADAVs16:
+ case MVE_VMLADAVs32:
+ case MVE_VMLADAVs8:
+ case MVE_VMLADAVu16:
+ case MVE_VMLADAVu32:
+ case MVE_VMLADAVu8:
+ case MVE_VMLADAVxs16:
+ case MVE_VMLADAVxs32:
+ case MVE_VMLADAVxs8:
+ case MVE_VMLALDAVas16:
+ case MVE_VMLALDAVas32:
+ case MVE_VMLALDAVau16:
+ case MVE_VMLALDAVau32:
+ case MVE_VMLALDAVaxs16:
+ case MVE_VMLALDAVaxs32:
+ case MVE_VMLALDAVs16:
+ case MVE_VMLALDAVs32:
+ case MVE_VMLALDAVu16:
+ case MVE_VMLALDAVu32:
+ case MVE_VMLALDAVxs16:
+ case MVE_VMLALDAVxs32:
+ case MVE_VMLSDAVas16:
+ case MVE_VMLSDAVas32:
+ case MVE_VMLSDAVas8:
+ case MVE_VMLSDAVaxs16:
+ case MVE_VMLSDAVaxs32:
+ case MVE_VMLSDAVaxs8:
+ case MVE_VMLSDAVs16:
+ case MVE_VMLSDAVs32:
+ case MVE_VMLSDAVs8:
+ case MVE_VMLSDAVxs16:
+ case MVE_VMLSDAVxs32:
+ case MVE_VMLSDAVxs8:
+ case MVE_VMLSLDAVas16:
+ case MVE_VMLSLDAVas32:
+ case MVE_VMLSLDAVaxs16:
+ case MVE_VMLSLDAVaxs32:
+ case MVE_VMLSLDAVs16:
+ case MVE_VMLSLDAVs32:
+ case MVE_VMLSLDAVxs16:
+ case MVE_VMLSLDAVxs32:
+ case MVE_VRMLALDAVHas32:
+ case MVE_VRMLALDAVHau32:
+ case MVE_VRMLALDAVHaxs32:
+ case MVE_VRMLALDAVHs32:
+ case MVE_VRMLALDAVHu32:
+ case MVE_VRMLALDAVHxs32:
+ case MVE_VRMLSLDAVHas32:
+ case MVE_VRMLSLDAVHaxs32:
+ case MVE_VRMLSLDAVHs32:
+ case MVE_VRMLSLDAVHxs32:
+ return true;
+ }
+ return false;
+ };
+
+ LLVMInitializeARMTargetInfo();
+ LLVMInitializeARMTarget();
+ LLVMInitializeARMTargetMC();
+
+ auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
+ std::string Error;
+ const Target *T = TargetRegistry::lookupTarget(TT, Error);
+ if (!T) {
+ dbgs() << Error;
+ return;
+ }
+
+ TargetOptions Options;
+ auto TM = std::unique_ptr<LLVMTargetMachine>(
+ static_cast<LLVMTargetMachine*>(
+ T->createTargetMachine(TT, "generic", "", Options, None, None,
+ CodeGenOpt::Default)));
+ ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+ std::string(TM->getTargetFeatureString()),
+ *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
+ const ARMBaseInstrInfo *TII = ST.getInstrInfo();
+ auto MII = TM->getMCInstrInfo();
+
+ for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
+ const MCInstrDesc &Desc = TII->get(i);
+
+ uint64_t Flags = Desc.TSFlags;
+ if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+ continue;
+
+ bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
+ ASSERT_EQ(HorizontalReduction(i), Valid)
+ << MII->getName(i)
+ << ": mismatched expectation for tail-predicated safety\n";
+ }
+}
+
TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
using namespace ARM;
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