[PATCH] D76727: [VectorCombine] transform bitcasted shuffle to narrower elements

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a reviewer: t.p.northover.
lebedev.ri added a comment.

>From reading through the `getCastInstrCost()`'s i don't think any backend
currently models it, but there's this comment in AArch64ISelLowering.cpp

  namespace llvm {
  
  namespace AArch64ISD {
  
  enum NodeType : unsigned {
  <...>
    /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
    /// world w.r.t vectors; which causes additional REV instructions to be
    /// generated to compensate for the byte-swapping. But sometimes we do
    /// need to re-interpret the data in SIMD vector registers in big-endian
    /// mode without emitting such REV instructions.
    NVCAST,

which is consistent with https://reviews.llvm.org/D40633#inline-355090 by @efriedma:

> On some targets, vector bitcasts aren't free (IIRC big-endian ARM is like this).




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76727/new/

https://reviews.llvm.org/D76727