[PATCH] D76732: [AMDGPU] Fix PC register mapping in wave32 mode

[Scott Linder via Phabricator via llvm-commits]

scott.linder created this revision.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, aprantl, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
scott.linder added reviewers: arsenm, t-tye, RamNalamothu.
scott.linder added a comment.

Sorry for missing this in the initial review, I caught it as I was rebasing my CFI changes and adding tests for wave32.


The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76732

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
  llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp


Index: llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
===================================================================
--- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+++ llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
@@ -75,10 +75,11 @@
       auto MRI = ST.getRegisterInfo();
       if (MRI) {
         // Wave32 Dwarf register mapping test numbers
-        // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+        // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
         // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
         // A0 => 2048, A255 => 2303
-        for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+        for (int llvmReg :
+             {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
           MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
           EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
         }
Index: llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
===================================================================
--- llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
+++ llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
@@ -65,10 +65,10 @@
     if (TM && TM->getMCRegisterInfo()) {
       auto MRI = TM->getMCRegisterInfo();
       // Wave32 Dwarf register mapping test numbers
-      // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+      // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
       // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
       // A0 => 2048, A255 => 2303
-      for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+      for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
         MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
       }
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -103,7 +103,7 @@
 def SP_REG : SIReg<"sp", 0>;
 
 // Pseudo-register to represent the program-counter DWARF register.
-def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 0]> {
+def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
   // There is no physical register corresponding to a "program counter", but
   // we need to encode the concept in debug information in order to represent
   // things like the return value in unwind information.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D76732.252430.patch
Type: text/x-patch
Size: 2468 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200324/2c289d23/attachment-0001.bin>