[PATCH] D76401: [PowerPC][AIX] ByVal formal argument support: single register.

[Sean Fertile via Phabricator via llvm-commits]

sfertile marked an inline comment as done.
sfertile added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/aix-cc-byval.ll:105
+; ASM32:        stw 3, 24(1)
+; ASM32-NEXT:   lbz 3, 24(1)
+; ASM32-NEXT:   blr
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cebowleratibm wrote:
> Curious to me that the optimizer didn't tidy up the stw/lbz.  It's ok for now but we need to ensure the param stack writes are being elided for performance.
For the 64-bit sub-targets we typically pass what would be ByVal on AIX as arrays of i64/i32 and coerce the values out which means no  gep/load in the IR.  On PPC32, we only pass the ByVals on the stack so no need to store the registers in the callee. The back end doesn't have anything to clean up the dead stores because we never produce them to begin with. 


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Comment at: llvm/test/CodeGen/PowerPC/aix-cc-byval.ll:362
+; 32BIT-NEXT:   liveins: $r3
+; 32BIT:        STW renamable $r3, 0, %fixed-stack.2 :: (store 4 into %fixed-stack.2, align 8)
+; 32BIT-DAG:    STW killed renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0)
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cebowleratibm wrote:
> dead stores at opt?  If this is temporary it probably warrants a comment in the expected output.
I think we have a 2 stage cleanup in relation to performance:
1) Extend the optimization that recognized how to pull the field from the register to work more generally 
2) Cleanup of the dead stores when we have extracted all the needed values from the register.

The problem is to big and general to specifically call out here. Every test in this file will need to be changed when we implement that.


Repository:
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https://reviews.llvm.org/D76401