[llvm] c84446f - [VectorCombine] add tests for bitcast (shuffle); NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-03-24T15:18:32-04:00
New Revision: c84446f4e9a86d7edfae8e18877e59f048733bee

URL: https://github.com/llvm/llvm-project/commit/c84446f4e9a86d7edfae8e18877e59f048733bee
DIFF: https://github.com/llvm/llvm-project/commit/c84446f4e9a86d7edfae8e18877e59f048733bee.diff

LOG: [VectorCombine] add tests for bitcast (shuffle); NFC

Added: 
    llvm/test/Transforms/VectorCombine/X86/shuffle.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll
new file mode 100644
index 000000000000..78d628615766
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=SSE2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=AVX2 | FileCheck %s --check-prefixes=CHECK,AVX
+
+define <16 x i8> @bitcast_shuf_narrow_element(<4 x i32> %v) {
+; CHECK-LABEL: @bitcast_shuf_narrow_element(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <16 x i8>
+; CHECK-NEXT:    ret <16 x i8> [[R]]
+;
+  %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r = bitcast <4 x i32> %shuf to <16 x i8>
+  ret <16 x i8> %r
+}
+
+define <4 x float> @bitcast_shuf_same_size(<4 x i32> %v) {
+; CHECK-LABEL: @bitcast_shuf_same_size(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <4 x float>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r = bitcast <4 x i32> %shuf to <4 x float>
+  ret <4 x float> %r
+}
+
+define <4 x i32> @bitcast_shuf_wide_element(<8 x i16> %v) {
+; CHECK-LABEL: @bitcast_shuf_wide_element(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <8 x i16> [[V:%.*]], <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:    [[R:%.*]] = bitcast <8 x i16> [[SHUF]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %shuf = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3>
+  %r = bitcast <8 x i16> %shuf to <4 x i32>
+  ret <4 x i32> %r
+}
+
+declare void @use(<4 x i32>)
+
+define <16 x i8> @bitcast_shuf_uses(<4 x i32> %v) {
+; CHECK-LABEL: @bitcast_shuf_uses(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    call void @use(<4 x i32> [[SHUF]])
+; CHECK-NEXT:    [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <16 x i8>
+; CHECK-NEXT:    ret <16 x i8> [[R]]
+;
+  %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  call void @use(<4 x i32> %shuf)
+  %r = bitcast <4 x i32> %shuf to <16 x i8>
+  ret <16 x i8> %r
+}
+
+define <2 x i64> @PR35454_1(<2 x i64> %v) {
+; CHECK-LABEL: @PR35454_1(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[PERMIL:%.*]] = shufflevector <4 x i32> [[BC]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <16 x i8>
+; CHECK-NEXT:    [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast <16 x i8> [[ADD]] to <4 x i32>
+; CHECK-NEXT:    [[PERMIL1:%.*]] = shufflevector <4 x i32> [[BC2]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[BC3:%.*]] = bitcast <4 x i32> [[PERMIL1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[BC3]]
+;
+  %bc = bitcast <2 x i64> %v to <4 x i32>
+  %permil = shufflevector <4 x i32> %bc, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bc1 = bitcast <4 x i32> %permil to <16 x i8>
+  %add = shl <16 x i8> %bc1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %bc2 = bitcast <16 x i8> %add to <4 x i32>
+  %permil1 = shufflevector <4 x i32> %bc2, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bc3 = bitcast <4 x i32> %permil1 to <2 x i64>
+  ret <2 x i64> %bc3
+}
+
+define <2 x i64> @PR35454_2(<2 x i64> %v) {
+; CHECK-LABEL: @PR35454_2(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[PERMIL:%.*]] = shufflevector <4 x i32> [[BC]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <8 x i16>
+; CHECK-NEXT:    [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast <8 x i16> [[ADD]] to <4 x i32>
+; CHECK-NEXT:    [[PERMIL1:%.*]] = shufflevector <4 x i32> [[BC2]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[BC3:%.*]] = bitcast <4 x i32> [[PERMIL1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[BC3]]
+;
+  %bc = bitcast <2 x i64> %v to <4 x i32>
+  %permil = shufflevector <4 x i32> %bc, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bc1 = bitcast <4 x i32> %permil to <8 x i16>
+  %add = shl <8 x i16> %bc1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  %bc2 = bitcast <8 x i16> %add to <4 x i32>
+  %permil1 = shufflevector <4 x i32> %bc2, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bc3 = bitcast <4 x i32> %permil1 to <2 x i64>
+  ret <2 x i64> %bc3
+}