[PATCH] D76356: [AMDGPU] Introduce more scratch registers in the ABI.

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 24 11:49:13 PDT 2020


rampitec added a comment.

In D76356#1939646 <https://reviews.llvm.org/D76356#1939646>, @arsenm wrote:

> In D76356#1939580 <https://reviews.llvm.org/D76356#1939580>, @rampitec wrote:
>
> > In D76356#1939493 <https://reviews.llvm.org/D76356#1939493>, @cdevadas wrote:
> >
> > > Thank you all for the comments.
> > >  I can see that there are concerns with the current split boundary (4 VGPRs together), considering the fact that we have wide VGPR uses in certain scenarios (image instructions).
> > >  But, like Matt mentioned, how frequently such scenarios occur?
> > >  Changing the split boundary to a large value would probably take away the whole purpose of this patch - reduce the CSR spills & try to ensure a better occupancy.
> >
> >
> > What will happen if you need to pass VReg_1024 into a function? It might not be a common case, but will it even work?
>
>
> It works, but that isn't changed by this patch. This is not changing the argument registers which are all still in v0-v31. I believe the largest argument type we pass in registers is <8 x i32>, and force <32 x i32> to be stack passed anyway


OK. What if such a register needs to be preserved by a caller? I guess there is no safe window for it, so it will be forced to spill. Then we will spill a whole huge register, not just a part of it, because we do not use sublane spilling (except to AGPRs), right?


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