[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension
Paolo Savini via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 24 05:21:02 PDT 2020
PaoloS marked 13 inline comments as done.
PaoloS added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:182
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Predicates = [HasStdExtZbb] in {
----------------
edward-jones wrote:
> Do these properties need to be specified, or do the values match the values which would be inferred by TableGen anyway (since all the DAG patterns are empty)?
Yes they are needed. TableGen gives error if they are not specified.
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https://reviews.llvm.org/D65649/new/
https://reviews.llvm.org/D65649
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