[PATCH] D76614: [PowerPC]: e500 target can't use lwsync, use msync instead

[Justin Hibbits via Phabricator via llvm-commits]

jhibbits created this revision.
jhibbits added a reviewer: PowerPC.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.

The e500 core has a silicon bug that triggers an illegal instruction
program trap on any sync other than msync.  Other cores will typically
ignore illegal sync types, and the documentation even implies that the
'illegal' bits are ignored.

Address this hardware deficiency by only using msync, like the PPC440.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76614

Files:
  llvm/lib/Target/PowerPC/PPC.td
  llvm/test/CodeGen/PowerPC/atomics-fences.ll


Index: llvm/test/CodeGen/PowerPC/atomics-fences.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/atomics-fences.ll
+++ llvm/test/CodeGen/PowerPC/atomics-fences.ll
@@ -1,6 +1,7 @@
 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=440 | FileCheck %s --check-prefix=PPC440
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=PPC440
 
 ; Fences
 define void @fence_acquire() {
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -452,7 +452,7 @@
 def : ProcessorModel<"e500", PPCE500Model,
                   [DirectiveE500,
                    FeatureICBT, FeatureBookE,
-                   FeatureISEL, FeatureMFTB, FeatureSPE]>;
+                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
 def : ProcessorModel<"e500mc", PPCE500mcModel,
                   [DirectiveE500mc,
                    FeatureSTFIWX, FeatureICBT, FeatureBookE,


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