[llvm] 25eb905 - [X86] getTargetShuffleAndZeroables - add insert_subvector(undef, sub, c) handling.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 21 12:12:34 PDT 2020
Author: Simon Pilgrim
Date: 2020-03-21T19:11:42Z
New Revision: 25eb9056d7fef511004952d176016948e3e09f40
URL: https://github.com/llvm/llvm-project/commit/25eb9056d7fef511004952d176016948e3e09f40
DIFF: https://github.com/llvm/llvm-project/commit/25eb9056d7fef511004952d176016948e3e09f40.diff
LOG: [X86] getTargetShuffleAndZeroables - add insert_subvector(undef, sub, c) handling.
We often widen xmm/ymm vectors to ymm/zmm by insertion into an undef base vector. By letting getTargetShuffleAndZeroables track the undef elts we can help avoid a lot of unnecessary cross-lane shuffles.
Fixes PR44694
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/haddsub-undef.ll
llvm/test/CodeGen/X86/var-permute-256.ll
llvm/test/CodeGen/X86/vector-reduce-mul.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c326315b38d0..5fe9a49108ba 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7118,6 +7118,24 @@ static bool getTargetShuffleAndZeroables(SDValue N, SmallVectorImpl<int> &Mask,
continue;
}
+ // INSERT_SUBVECTOR - to widen vectors we often insert them into UNDEF
+ // base vectors.
+ if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
+ SDValue Vec = V.getOperand(0);
+ int NumVecElts = Vec.getValueType().getVectorNumElements();
+ if (Vec.isUndef() && Size == NumVecElts) {
+ auto *CIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
+ int NumSubElts = V.getOperand(1).getValueType().getVectorNumElements();
+ if (CIdx && CIdx->getAPIntValue().ule(NumVecElts - NumSubElts)) {
+ int Idx = CIdx->getZExtValue();
+ if (M < Idx || (Idx + NumSubElts) <= M) {
+ KnownUndef.setBit(i);
+ }
+ }
+ }
+ continue;
+ }
+
// Attempt to extract from the source's constant bits.
if (IsSrcConstant[SrcIdx]) {
if (UndefSrcElts[SrcIdx][M])
diff --git a/llvm/test/CodeGen/X86/haddsub-undef.ll b/llvm/test/CodeGen/X86/haddsub-undef.ll
index 7b7574b9ccf6..83e7eb4c27b7 100644
--- a/llvm/test/CodeGen/X86/haddsub-undef.ll
+++ b/llvm/test/CodeGen/X86/haddsub-undef.ll
@@ -823,9 +823,7 @@ define <4 x double> @PR44694(<4 x double> %0, <4 x double> %1) {
; AVX: # %bb.0:
; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
-; AVX-NEXT: vunpcklpd {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
-; AVX-NEXT: vshufpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[3],ymm0[3]
-; AVX-NEXT: vaddpd %ymm0, %ymm2, %ymm0
+; AVX-NEXT: vhaddpd %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
%3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
%4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
diff --git a/llvm/test/CodeGen/X86/var-permute-256.ll b/llvm/test/CodeGen/X86/var-permute-256.ll
index d1594eddf444..4c04219b3883 100644
--- a/llvm/test/CodeGen/X86/var-permute-256.ll
+++ b/llvm/test/CodeGen/X86/var-permute-256.ll
@@ -558,29 +558,27 @@ define <4 x i64> @var_shuffle_v4i64_from_v2i64(<2 x i64> %v, <4 x i64> %indices)
; XOP-LABEL: var_shuffle_v4i64_from_v2i64:
; XOP: # %bb.0:
; XOP-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; XOP-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm3
+; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; XOP-NEXT: vextractf128 $1, %ymm1, %xmm1
; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm1
-; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
-; XOP-NEXT: vpermil2pd $0, %ymm1, %ymm2, %ymm0, %ymm0
+; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; XOP-NEXT: vpermil2pd $0, %ymm1, %ymm0, %ymm0, %ymm0
; XOP-NEXT: retq
;
; AVX1-LABEL: var_shuffle_v4i64_from_v2i64:
; AVX1: # %bb.0:
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
-; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4
-; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
+; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
+; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -590,8 +588,7 @@ define <4 x i64> @var_shuffle_v4i64_from_v2i64(<2 x i64> %v, <4 x i64> %indices)
; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2]
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm1, %ymm2
-; AVX2-NEXT: vpermpd {{.*#+}} ymm3 = ymm0[2,3,2,3]
-; AVX2-NEXT: vpermilpd %ymm1, %ymm3, %ymm3
+; AVX2-NEXT: vpermilpd %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,0,1]
; AVX2-NEXT: vpermilpd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vblendvpd %ymm2, %ymm3, %ymm0, %ymm0
@@ -984,29 +981,27 @@ define <4 x double> @var_shuffle_v4f64_from_v2f64(<2 x double> %v, <4 x i64> %in
; XOP-LABEL: var_shuffle_v4f64_from_v2f64:
; XOP: # %bb.0:
; XOP-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; XOP-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm3
+; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; XOP-NEXT: vextractf128 $1, %ymm1, %xmm1
; XOP-NEXT: vpaddq %xmm1, %xmm1, %xmm1
-; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
-; XOP-NEXT: vpermil2pd $0, %ymm1, %ymm2, %ymm0, %ymm0
+; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; XOP-NEXT: vpermil2pd $0, %ymm1, %ymm0, %ymm0, %ymm0
; XOP-NEXT: retq
;
; AVX1-LABEL: var_shuffle_v4f64_from_v2f64:
; AVX1: # %bb.0:
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
-; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4
-; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
-; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
+; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
+; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -1016,8 +1011,7 @@ define <4 x double> @var_shuffle_v4f64_from_v2f64(<2 x double> %v, <4 x i64> %in
; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2]
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm1, %ymm2
-; AVX2-NEXT: vpermpd {{.*#+}} ymm3 = ymm0[2,3,2,3]
-; AVX2-NEXT: vpermilpd %ymm1, %ymm3, %ymm3
+; AVX2-NEXT: vpermilpd %ymm1, %ymm0, %ymm3
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,0,1]
; AVX2-NEXT: vpermilpd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vblendvpd %ymm2, %ymm3, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-mul.ll b/llvm/test/CodeGen/X86/vector-reduce-mul.ll
index 39b189c157ce..9bdd722f6402 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-mul.ll
@@ -2011,9 +2011,9 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX2-NEXT: vpmullw %xmm2, %xmm3, %xmm2
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vpmullw %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
@@ -2099,9 +2099,9 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX512DQ-NEXT: vpmullw %xmm2, %xmm3, %xmm2
; AVX512DQ-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; AVX512DQ-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512DQ-NEXT: vpmullw %xmm2, %xmm1, %xmm1
-; AVX512DQ-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
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