[llvm] f00a4b5 - [InstCombine][X86] simplifyX86immShift - remove ConstantAggregateZero handling. NFC.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sat Mar 21 04:31:14 PDT 2020


Author: Simon Pilgrim
Date: 2020-03-21T11:30:44Z
New Revision: f00a4b531a5996fc79d815d62d8b34cff8e5c935

URL: https://github.com/llvm/llvm-project/commit/f00a4b531a5996fc79d815d62d8b34cff8e5c935
DIFF: https://github.com/llvm/llvm-project/commit/f00a4b531a5996fc79d815d62d8b34cff8e5c935.diff

LOG: [InstCombine][X86] simplifyX86immShift - remove ConstantAggregateZero handling. NFC.

The llvm::computeKnownBits path now handles this.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 25872e85616a..d4fc6594f28d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -425,27 +425,23 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
   }
 
   // Simplify if count is constant vector.
-  auto CAZ = dyn_cast<ConstantAggregateZero>(Amt);
   auto CDV = dyn_cast<ConstantDataVector>(Amt);
-  if (!CAZ && !CDV)
+  if (!CDV)
     return nullptr;
 
+  // SSE2/AVX2 uses all the first 64-bits of the 128-bit vector
+  // operand to compute the shift amount.
+  assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 &&
+         cast<VectorType>(AmtVT)->getElementType() == SVT &&
+         "Unexpected shift-by-scalar type");
+
+  // Concatenate the sub-elements to create the 64-bit value.
   APInt Count(64, 0);
-  if (CDV) {
-    // SSE2/AVX2 uses all the first 64-bits of the 128-bit vector
-    // operand to compute the shift amount.
-    auto VT = cast<VectorType>(CDV->getType());
-    unsigned BitWidth = VT->getElementType()->getPrimitiveSizeInBits();
-    assert((64 % BitWidth) == 0 && "Unexpected packed shift size");
-    unsigned NumSubElts = 64 / BitWidth;
-
-    // Concatenate the sub-elements to create the 64-bit value.
-    for (unsigned i = 0; i != NumSubElts; ++i) {
-      unsigned SubEltIdx = (NumSubElts - 1) - i;
-      auto SubElt = cast<ConstantInt>(CDV->getElementAsConstant(SubEltIdx));
-      Count <<= BitWidth;
-      Count |= SubElt->getValue().zextOrTrunc(64);
-    }
+  for (unsigned i = 0, NumSubElts = 64 / BitWidth; i != NumSubElts; ++i) {
+    unsigned SubEltIdx = (NumSubElts - 1) - i;
+    auto SubElt = cast<ConstantInt>(CDV->getElementAsConstant(SubEltIdx));
+    Count <<= BitWidth;
+    Count |= SubElt->getValue().zextOrTrunc(64);
   }
 
   // If shift-by-zero then just return the original value.


        


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