[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

This seems like a good approach.

Do we have any tests for it? I notice a simple fixed-width argument test blows up (unless I'm making a mistake on my side):

  ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
  ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-isel-sve-vector-bits=512 < %s | FileCheck %s
  
  define <16 x float> @fadd_float_512b(<16 x float> %a, <16 x float> %b) {
  ; CHECK-LABEL: fadd_float_512b:
  ; CHECK:       // %bb.0:
  ; CHECK-NEXT:    fadd z0.s, z0.s, z1.s
  ; CHECK-NEXT:    ret
    %fadd = fadd <16 x float> %a, %b
    ret <16 x float> %fadd
  }

I have a somewhat hacky solution to the calling convention issues, which I'll share soon. Hoping for a better solution though, since mine is clunky...


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https://reviews.llvm.org/D71767