[llvm] a09ff56 - [Tests] Regenerate some test checks; NFC
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 20 04:07:08 PDT 2020
Author: Nikita Popov
Date: 2020-03-20T12:06:53+01:00
New Revision: a09ff56b5b5edc3aef0e2f572f9ffd1c4deb8e08
URL: https://github.com/llvm/llvm-project/commit/a09ff56b5b5edc3aef0e2f572f9ffd1c4deb8e08
DIFF: https://github.com/llvm/llvm-project/commit/a09ff56b5b5edc3aef0e2f572f9ffd1c4deb8e08.diff
LOG: [Tests] Regenerate some test checks; NFC
Added:
Modified:
llvm/test/Analysis/ValueTracking/knownnonzero-shift.ll
llvm/test/Transforms/GVN/PRE/volatile.ll
llvm/test/Transforms/InstSimplify/assume.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/ValueTracking/knownnonzero-shift.ll b/llvm/test/Analysis/ValueTracking/knownnonzero-shift.ll
index e59d19cc2e26..c91e53157840 100644
--- a/llvm/test/Analysis/ValueTracking/knownnonzero-shift.ll
+++ b/llvm/test/Analysis/ValueTracking/knownnonzero-shift.ll
@@ -1,12 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instsimplify -S < %s | FileCheck %s
-; CHECK-LABEL: @test
define i1 @test(i8 %p, i8* %pq) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT: ret i1 true
+;
%q = load i8, i8* %pq, !range !0 ; %q is known nonzero; no known bits
%1 = shl i8 %p, %q ; because %q is nonzero, %1[0] is known to be zero.
%2 = and i8 %1, 1
%x = icmp eq i8 %2, 0
- ; CHECK: ret i1 true
ret i1 %x
}
diff --git a/llvm/test/Transforms/GVN/PRE/volatile.ll b/llvm/test/Transforms/GVN/PRE/volatile.ll
index ccc5bbfa48e4..552f8dce7833 100644
--- a/llvm/test/Transforms/GVN/PRE/volatile.ll
+++ b/llvm/test/Transforms/GVN/PRE/volatile.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; Tests that check our handling of volatile instructions encountered
; when scanning for dependencies
; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
@@ -5,9 +6,11 @@
; Check that we can bypass a volatile load when searching
; for dependencies of a non-volatile load
define i32 @test1(i32* nocapture %p, i32* nocapture %q) {
-; CHECK-LABEL: test1
-; CHECK: %0 = load volatile i32, i32* %q
-; CHECK-NEXT: ret i32 0
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT: ret i32 0
+;
entry:
%x = load i32, i32* %p
load volatile i32, i32* %q
@@ -16,13 +19,16 @@ entry:
ret i32 %add
}
-; We can not value forward if the query instruction is
+; We can not value forward if the query instruction is
; volatile, this would be (in effect) removing the volatile load
define i32 @test2(i32* nocapture %p, i32* nocapture %q) {
-; CHECK-LABEL: test2
-; CHECK: %x = load i32, i32* %p
-; CHECK-NEXT: %y = load volatile i32, i32* %p
-; CHECK-NEXT: %add = sub i32 %y, %x
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]]
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
+; CHECK-NEXT: ret i32 [[ADD]]
+;
entry:
%x = load i32, i32* %p
%y = load volatile i32, i32* %p
@@ -33,10 +39,14 @@ entry:
; If the query instruction is itself volatile, we *cannot*
; reorder it even if p and q are noalias
define i32 @test3(i32* noalias nocapture %p, i32* noalias nocapture %q) {
-; CHECK-LABEL: test3
-; CHECK: %x = load i32, i32* %p
-; CHECK-NEXT: %0 = load volatile i32, i32* %q
-; CHECK-NEXT: %y = load volatile i32, i32* %p
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]]
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
+; CHECK-NEXT: ret i32 [[ADD]]
+;
entry:
%x = load i32, i32* %p
load volatile i32, i32* %q
@@ -45,14 +55,18 @@ entry:
ret i32 %add
}
-; If an encountered instruction is both volatile and ordered,
-; we need to use the strictest ordering of either. In this
+; If an encountered instruction is both volatile and ordered,
+; we need to use the strictest ordering of either. In this
; case, the ordering prevents forwarding.
define i32 @test4(i32* noalias nocapture %p, i32* noalias nocapture %q) {
-; CHECK-LABEL: test4
-; CHECK: %x = load i32, i32* %p
-; CHECK-NEXT: %0 = load atomic volatile i32, i32* %q seq_cst
-; CHECK-NEXT: %y = load atomic i32, i32* %p seq_cst
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic volatile i32, i32* [[Q:%.*]] seq_cst, align 4
+; CHECK-NEXT: [[Y:%.*]] = load atomic i32, i32* [[P]] seq_cst, align 4
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
+; CHECK-NEXT: ret i32 [[ADD]]
+;
entry:
%x = load i32, i32* %p
load atomic volatile i32, i32* %q seq_cst, align 4
@@ -63,9 +77,11 @@ entry:
; Value forwarding from a volatile load is perfectly legal
define i32 @test5(i32* nocapture %p, i32* nocapture %q) {
-; CHECK-LABEL: test5
-; CHECK: %x = load volatile i32, i32* %p
-; CHECK-NEXT: ret i32 0
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[P:%.*]]
+; CHECK-NEXT: ret i32 0
+;
entry:
%x = load volatile i32, i32* %p
%y = load i32, i32* %p
@@ -75,11 +91,19 @@ entry:
; Does cross block redundancy elimination work with volatiles?
define i32 @test6(i32* noalias nocapture %p, i32* noalias nocapture %q) {
-; CHECK-LABEL: test6
-; CHECK: %y1 = load i32, i32* %p
-; CHECK-LABEL: header
-; CHECK: %x = load volatile i32, i32* %q
-; CHECK-NEXT: %add = sub i32 %y1, %x
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: call void @use(i32 [[Y1]])
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y1]], [[X]]
+; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
+; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 0
+;
entry:
%y1 = load i32, i32* %p
call void @use(i32 %y1)
@@ -96,15 +120,25 @@ exit:
; Does cross block PRE work with volatiles?
define i32 @test7(i1 %c, i32* noalias nocapture %p, i32* noalias nocapture %q) {
-; CHECK-LABEL: test7
-; CHECK-LABEL: entry.header_crit_edge:
-; CHECK: %y.pre = load i32, i32* %p
-; CHECK-LABEL: skip:
-; CHECK: %y1 = load i32, i32* %p
-; CHECK-LABEL: header:
-; CHECK: %y = phi i32
-; CHECK-NEXT: %x = load volatile i32, i32* %q
-; CHECK-NEXT: %add = sub i32 %y, %x
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[ENTRY_HEADER_CRIT_EDGE:%.*]], label [[SKIP:%.*]]
+; CHECK: entry.header_crit_edge:
+; CHECK-NEXT: [[Y_PRE:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: skip:
+; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P]]
+; CHECK-NEXT: call void @use(i32 [[Y1]])
+; CHECK-NEXT: br label [[HEADER]]
+; CHECK: header:
+; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[SKIP]] ]
+; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
+; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
+; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 0
+;
entry:
br i1 %c, label %header, label %skip
skip:
@@ -124,15 +158,26 @@ exit:
; Another volatile PRE case - two paths through a loop
; load in preheader, one path read only, one not
define i32 @test8(i1 %b, i1 %c, i32* noalias %p, i32* noalias %q) {
-; CHECK-LABEL: test8
-; CHECK-LABEL: entry
-; CHECK: %y1 = load i32, i32* %p
-; CHECK-LABEL: header:
-; CHECK: %y = phi i32
-; CHECK-NEXT: %x = load volatile i32, i32* %q
-; CHECK-NOT: load
-; CHECK-LABEL: skip.header_crit_edge:
-; CHECK: %y.pre = load i32, i32* %p
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT: call void @use(i32 [[Y1]])
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE:%.*]], [[SKIP_HEADER_CRIT_EDGE:%.*]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT: call void @use(i32 [[Y]])
+; CHECK-NEXT: br i1 [[B:%.*]], label [[SKIP:%.*]], label [[HEADER]]
+; CHECK: skip:
+; CHECK-NEXT: call void @clobber(i32* [[P]], i32* [[Q]])
+; CHECK-NEXT: br i1 [[C:%.*]], label [[SKIP_HEADER_CRIT_EDGE]], label [[EXIT:%.*]]
+; CHECK: skip.header_crit_edge:
+; CHECK-NEXT: [[Y_PRE]] = load i32, i32* [[P]]
+; CHECK-NEXT: br label [[HEADER]]
+; CHECK: exit:
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
+; CHECK-NEXT: ret i32 [[ADD]]
+;
entry:
%y1 = load i32, i32* %p
call void @use(i32 %y1)
@@ -143,7 +188,7 @@ header:
call void @use(i32 %y)
br i1 %b, label %skip, label %header
skip:
- ; escaping the arguments is explicitly required since we marked
+ ; escaping the arguments is explicitly required since we marked
; them noalias
call void @clobber(i32* %p, i32* %q)
br i1 %c, label %header, label %exit
@@ -153,13 +198,15 @@ exit:
}
define i32 @test9(i32* %V) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[LOAD:%.*]] = load volatile i32, i32* [[V:%.*]], !range !0
+; CHECK-NEXT: ret i32 0
+;
entry:
%load = load volatile i32, i32* %V, !range !0
ret i32 %load
}
-; CHECK-LABEL: test9
-; CHECK: load volatile
-; CHECK: ret i32 0
declare void @use(i32) readonly
declare void @clobber(i32* %p, i32* %q)
diff --git a/llvm/test/Transforms/InstSimplify/assume.ll b/llvm/test/Transforms/InstSimplify/assume.ll
index 157d8de8fcf8..a43f90adee37 100644
--- a/llvm/test/Transforms/InstSimplify/assume.ll
+++ b/llvm/test/Transforms/InstSimplify/assume.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instsimplify -S < %s 2>&1 -pass-remarks-analysis=.* | FileCheck %s
; Verify that warnings are emitted for the 2nd and 3rd tests.
@@ -9,7 +9,7 @@
define void @test1() {
; CHECK-LABEL: @test1(
-; CHECK: ret void
+; CHECK-NEXT: ret void
;
call void @llvm.assume(i1 1)
ret void
@@ -17,7 +17,7 @@ define void @test1() {
}
; The alloca guarantees that the low bits of %a are zero because of alignment.
-; The assume says the opposite. The assume is processed last, so that's the
+; The assume says the opposite. The assume is processed last, so that's the
; return value. There's no way to win (we can't undo transforms that happened
; based on half-truths), so just don't crash.
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