[llvm] baa6f6a - Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
Adrian Kuegel via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 20 03:04:51 PDT 2020
Author: Adrian Kuegel
Date: 2020-03-20T11:02:50+01:00
New Revision: baa6f6a7828a46c37b96227282938717220f8b34
URL: https://github.com/llvm/llvm-project/commit/baa6f6a7828a46c37b96227282938717220f8b34
DIFF: https://github.com/llvm/llvm-project/commit/baa6f6a7828a46c37b96227282938717220f8b34.diff
LOG: Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
This reverts commit e9f22fd4293a65bcdcf1b18b91c72f63e5e9e45b.
When building with -DLLVM_USE_SANITIZER="Thread", check-llvm has 70
failing tests with this revision, and 29 without this revision.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/utils/TableGen/RegisterBankEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
index 8a8d3ce20040..f528d1a46012 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
@@ -29,23 +29,18 @@ class RegisterBank {
private:
unsigned ID;
const char *Name;
- const unsigned *Sizes;
+ unsigned Size;
BitVector ContainedRegClasses;
- /// HwMode of the target. Not initialized by the constructor, initialized
- /// within generated RegisterBankInfo class constructor.
- unsigned HwMode;
-
- /// Sentinel values used to recognize register bank not properly
+ /// Sentinel value used to recognize register bank not properly
/// initialized yet.
static const unsigned InvalidID;
- static const unsigned InvalidHwMode;
/// Only the RegisterBankInfo can initialize RegisterBank properly.
friend RegisterBankInfo;
public:
- RegisterBank(unsigned ID, const char *Name, const unsigned *Sizes,
+ RegisterBank(unsigned ID, const char *Name, unsigned Size,
const uint32_t *CoveredClasses, unsigned NumRegClasses);
/// Get the identifier of this register bank.
@@ -56,7 +51,7 @@ class RegisterBank {
const char *getName() const { return Name; }
/// Get the maximal size in bits that fits in this register bank.
- unsigned getSize() const { return Sizes[HwMode]; }
+ unsigned getSize() const { return Size; }
/// Check whether this instance is ready to be used.
bool isValid() const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index b86d2d10322f..8725d96efd82 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -415,8 +415,7 @@ class RegisterBankInfo {
/// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
/// RegisterBank instances.
- RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks,
- unsigned HwMode);
+ RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
/// This constructor is meaningless.
/// It just provides a default constructor that can be used at link time
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
index 54e5d48edf27..fc9c802693ab 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -19,12 +19,11 @@
using namespace llvm;
const unsigned RegisterBank::InvalidID = UINT_MAX;
-const unsigned RegisterBank::InvalidHwMode = UINT_MAX;
RegisterBank::RegisterBank(
- unsigned ID, const char *Name, const unsigned *Sizes,
+ unsigned ID, const char *Name, unsigned Size,
const uint32_t *CoveredClasses, unsigned NumRegClasses)
- : ID(ID), Name(Name), Sizes(Sizes), HwMode(InvalidHwMode) {
+ : ID(ID), Name(Name), Size(Size) {
ContainedRegClasses.resize(NumRegClasses);
ContainedRegClasses.setBitsInMask(CoveredClasses);
}
@@ -64,8 +63,7 @@ bool RegisterBank::covers(const TargetRegisterClass &RC) const {
}
bool RegisterBank::isValid() const {
- return ID != InvalidID && Name != nullptr && Sizes != nullptr &&
- HwMode != InvalidID &&
+ return ID != InvalidID && Name != nullptr && Size != 0 &&
// A register bank that does not cover anything is useless.
!ContainedRegClasses.empty();
}
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 3a8d0a9d3c4f..255ea693b5c4 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -56,11 +56,8 @@ const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
// RegisterBankInfo implementation.
//------------------------------------------------------------------------------
RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
- unsigned NumRegBanks, unsigned HwMode)
+ unsigned NumRegBanks)
: RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
- // Initialize HwMode for all RegBanks
- for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx)
- RegBanks[Idx]->HwMode = HwMode;
#ifndef NDEBUG
for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
index 9db3107da073..bd3b95a98b9f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
@@ -22,5 +22,5 @@
using namespace llvm;
-RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
- : RISCVGenRegisterBankInfo(HwMode) {}
+RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)
+ : RISCVGenRegisterBankInfo() {}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
index 71dddd28380d..05fac992734d 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
@@ -31,7 +31,7 @@ class RISCVGenRegisterBankInfo : public RegisterBankInfo {
/// This class provides the information for the target register banks.
class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
public:
- RISCVRegisterBankInfo(unsigned HwMode);
+ RISCVRegisterBankInfo(const TargetRegisterInfo &TRI);
};
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 9815a7852689..47a48c820a29 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -56,7 +56,7 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
Legalizer.reset(new RISCVLegalizerInfo(*this));
- auto *RBI = new RISCVRegisterBankInfo(getHwMode());
+ auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
RegBankInfo.reset(RBI);
InstSelector.reset(createRISCVInstructionSelector(
*static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 5d0751d14451..586f857b1fb0 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -37,12 +37,12 @@ class RegisterBank {
/// The register classes that are covered by the register bank.
RegisterClassesTy RCs;
- /// The register classes with the largest register size for each HwMode.
- std::vector<const CodeGenRegisterClass *> RCsWithLargestRegSize;
+ /// The register class with the largest register size.
+ const CodeGenRegisterClass *RCWithLargestRegsSize;
public:
- RegisterBank(const Record &TheDef, unsigned NumModeIds)
- : TheDef(TheDef), RCs(), RCsWithLargestRegSize(NumModeIds) {}
+ RegisterBank(const Record &TheDef)
+ : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
/// Get the human-readable name for the bank.
StringRef getName() const { return TheDef.getValueAsString("Name"); }
@@ -54,10 +54,6 @@ class RegisterBank {
return (TheDef.getName() + "CoverageData").str();
}
- std::string getSizesArrayName() const {
- return (TheDef.getName() + "Sizes").str();
- }
-
/// Get the name of the global instance variable.
StringRef getInstanceVarName() const { return TheDef.getName(); }
@@ -87,20 +83,18 @@ class RegisterBank {
// register size anywhere (we could sum the sizes of the subregisters
// but there may be additional bits too) and we can't derive it from
// the VT's reliably due to Untyped.
- unsigned NumModeIds = RCsWithLargestRegSize.size();
- for (unsigned M = 0; M < NumModeIds; ++M) {
- if (RCsWithLargestRegSize[M] == nullptr)
- RCsWithLargestRegSize[M] = RC;
- else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize <
- RC->RSI.get(M).SpillSize)
- RCsWithLargestRegSize[M] = RC;
- assert(RCsWithLargestRegSize[M] && "RC was nullptr?");
- }
+ if (RCWithLargestRegsSize == nullptr)
+ RCWithLargestRegsSize = RC;
+ else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize <
+ RC->RSI.get(DefaultMode).SpillSize)
+ RCWithLargestRegsSize = RC;
+ assert(RCWithLargestRegsSize && "RC was nullptr?");
+
RCs.emplace_back(RC);
}
- const CodeGenRegisterClass *getRCWithLargestRegsSize(unsigned HwMode) const {
- return RCsWithLargestRegSize[HwMode];
+ const CodeGenRegisterClass *getRCWithLargestRegsSize() const {
+ return RCWithLargestRegsSize;
}
iterator_range<typename RegisterClassesTy::const_iterator>
@@ -153,7 +147,7 @@ void RegisterBankEmitter::emitBaseClassDefinition(
OS << "private:\n"
<< " static RegisterBank *RegBanks[];\n\n"
<< "protected:\n"
- << " " << TargetName << "GenRegisterBankInfo(unsigned HwMode = 0);\n"
+ << " " << TargetName << "GenRegisterBankInfo();\n"
<< "\n";
}
@@ -219,7 +213,6 @@ void RegisterBankEmitter::emitBaseClassImplementation(
raw_ostream &OS, StringRef TargetName,
std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
- const CodeGenHwModes &CGH = Target.getHwModes();
OS << "namespace llvm {\n"
<< "namespace " << TargetName << " {\n";
@@ -247,30 +240,14 @@ void RegisterBankEmitter::emitBaseClassImplementation(
}
OS << "\n";
- unsigned NumModeIds = CGH.getNumModeIds();
- for (const auto &Bank : Banks) {
- OS << "const unsigned " << Bank.getSizesArrayName() << "[] = {\n";
- for (unsigned M = 0; M < NumModeIds; ++M) {
- const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(M);
- unsigned Size = RC.RSI.get(M).SpillSize;
- OS << " // Mode = " << M << " (";
- if (M == 0)
- OS << "Default";
- else
- OS << CGH.getMode(M).Name;
- OS << ")\n";
- OS << " " << Size << ",\n";
- }
- OS << "};\n";
- }
- OS << "\n";
-
for (const auto &Bank : Banks) {
std::string QualifiedBankID =
(TargetName + "::" + Bank.getEnumeratorName()).str();
+ const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize();
+ unsigned Size = RC.RSI.get(DefaultMode).SpillSize;
OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName()
- << "\", /* Sizes */ " << Bank.getInstanceVarName() << "Sizes, "
+ << "\", /* Size */ " << Size << ", "
<< "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
<< ", /* NumRegClasses */ "
<< RegisterClassHierarchy.getRegClasses().size() << ");\n";
@@ -285,9 +262,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
OS << "};\n\n";
OS << TargetName << "GenRegisterBankInfo::" << TargetName
- << "GenRegisterBankInfo(unsigned HwMode)\n"
+ << "GenRegisterBankInfo()\n"
<< " : RegisterBankInfo(RegBanks, " << TargetName
- << "::NumRegisterBanks, HwMode) {\n"
+ << "::NumRegisterBanks) {\n"
<< " // Assert that RegBank indices match their ID's\n"
<< "#ifndef NDEBUG\n"
<< " unsigned Index = 0;\n"
@@ -301,12 +278,11 @@ void RegisterBankEmitter::emitBaseClassImplementation(
void RegisterBankEmitter::run(raw_ostream &OS) {
StringRef TargetName = Target.getName();
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
- const CodeGenHwModes &CGH = Target.getHwModes();
std::vector<RegisterBank> Banks;
for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
- RegisterBank Bank(*V, CGH.getNumModeIds());
+ RegisterBank Bank(*V);
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
More information about the llvm-commits
mailing list