shchenz added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4478
+ }
+
+ // We can do special handling for pattern like this.
----------------
For special case, form a new Imm, like:
```
APInt Res(64, Imm64);
ClearBits = Res.countLeadingZeros();
if (ClearBits != 0) {
// change pattern |0001111100000011111111|
// to |1111111100000011111111|
APInt Mask = APInt::getBitsSet(64, 64 - ClearBits, 64);
Res = Res | Mask;
Imm64 = Res.getZExtValue();
}
```
And pass new Imm64 and ClearBits to normal case, I think logic here maybe a little simple?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D71831/new/
https://reviews.llvm.org/D71831