[PATCH] D75138: [WIP][AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions

Scott Linder via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 19 13:10:39 PDT 2020 

This revision was automatically updated to reflect the committed changes.
Closed by commit rG60b1967c3933: [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions (authored by scott.linder).

Changed prior to commit:
  https://reviews.llvm.org/D75138?vs=250925&id=251459#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75138/new/

https://reviews.llvm.org/D75138

Files:
  llvm/docs/AMDGPUUsage.rst
  llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
  llvm/test/CodeGen/AMDGPU/addrspacecast.ll
  llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
  llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
  llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/call-constant.ll
  llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
  llvm/test/CodeGen/AMDGPU/cc-update.ll
  llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/extload-private.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
  llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
  llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
  llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
  llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
  llvm/test/CodeGen/AMDGPU/function-returns.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/ipra.ll
  llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
  llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll
  llvm/test/CodeGen/AMDGPU/load-hi16.ll
  llvm/test/CodeGen/AMDGPU/load-lo16.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/mesa3d.ll
  llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
  llvm/test/CodeGen/AMDGPU/misched-killflags.mir
  llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
  llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
  llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
  llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
  llvm/test/CodeGen/AMDGPU/private-element-size.ll
  llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
  llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
  llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
  llvm/test/CodeGen/AMDGPU/scratch-simple.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
  llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr.ll
  llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
  llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  llvm/test/CodeGen/AMDGPU/spill-m0.ll
  llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
  llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
  llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
  llvm/test/CodeGen/AMDGPU/stack-realign.ll
  llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  llvm/test/CodeGen/AMDGPU/store-hi16.ll
  llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
  llvm/test/CodeGen/AMDGPU/subvector-test.mir
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
  llvm/test/CodeGen/AMDGPU/wqm.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
  llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
  llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
  llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
  llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
  llvm/test/DebugInfo/AMDGPU/variable-locations.ll

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