[PATCH] D76445: [RISCV][GlobalISel] Add tests for selecting ALU GPR instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, simoncook, Joe.
Herald added subscribers: llvm-commits, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, johnrusso, rbar, rovka.
Herald added a project: LLVM.

The instruction selection patterns required for ALU GPR instructions have already been automatically imported from existing TableGen descriptions - this patch simply adds testing for them.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76445

Files:
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D76445.251435.patch
Type: text/x-patch
Size: 11878 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200319/008e3711/attachment-0001.bin>