[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Is there any particular reason to lower ISD::AND on a fixed vector to an intrinsic, as opposed to simply lowering it to an ISD::AND on a scalable vector?  The patterns should mostly be there to make it work.

Otherwise, the general approach seems reasonable.


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  https://reviews.llvm.org/D71767/new/

https://reviews.llvm.org/D71767