[PATCH] D75833: [RISCV] Support RISC-V ELF attribute section in llvm-readobj

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.


================
Comment at: llvm/tools/llvm-readobj/ELFDumper.cpp:2676
+      Obj->getHeader()->e_machine != EM_RISCV) {
     W.startLine() << "Attributes not implemented.\n";
     return;
----------------
jhenderson wrote:
> HsiangKai wrote:
> > jhenderson wrote:
> > > Is there a test case for this line?
> > No, it is not related to this patch.
> Yes it is. The behaviour has gone from "not EM_ARM" to "not EM_ARM and not EM_RISCV", which means the code here is now exercised differently. Again, you could add a prerequisite test that shows that non-ARM architectures hit this. Then, in this patch, you would remove the EM_RISCV case.
I found `printAttributes` only called under EM_ARM and EM_RISCV. I add an assertion in `printAttributes` to ensure it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75833/new/

https://reviews.llvm.org/D75833