[llvm] 49bdfd8 - [InstSimplify] Add missing vector masked add tests to show lack of DemandedElts support

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-03-18T21:04:54Z
New Revision: 49bdfd888d38ca1112d58574902566347da3ab6a

URL: https://github.com/llvm/llvm-project/commit/49bdfd888d38ca1112d58574902566347da3ab6a
DIFF: https://github.com/llvm/llvm-project/commit/49bdfd888d38ca1112d58574902566347da3ab6a.diff

LOG: [InstSimplify] Add missing vector masked add tests to show lack of DemandedElts support

Added: 
    

Modified: 
    llvm/test/Transforms/InstSimplify/add-mask.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstSimplify/add-mask.ll b/llvm/test/Transforms/InstSimplify/add-mask.ll
index e30a35f53127..fe384e338b8f 100644
--- a/llvm/test/Transforms/InstSimplify/add-mask.ll
+++ b/llvm/test/Transforms/InstSimplify/add-mask.ll
@@ -1,9 +1,9 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instsimplify < %s | FileCheck %s
 
-define i1 @test(i32 %a) {
-; CHECK-LABEL: @test(
-; CHECK:         ret i1 false
+define i1 @test1(i32 %a) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret i1 false
 ;
   %rhs = add i32 %a, -1
   %and = and i32 %a, %rhs
@@ -11,9 +11,24 @@ define i1 @test(i32 %a) {
   ret i1 %res
 }
 
+define i1 @test1v(<2 x i32> %a) {
+; CHECK-LABEL: @test1v(
+; CHECK-NEXT:    [[RHS:%.*]] = add <2 x i32> [[A:%.*]], <i32 -1, i32 0>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A]], [[RHS]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 0
+; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[EXT]], 1
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %rhs = add <2 x i32> %a, <i32 -1, i32 0>
+  %and = and <2 x i32> %a, %rhs
+  %ext = extractelement <2 x i32> %and, i32 0
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}
+
 define i1 @test2(i32 %a) {
 ; CHECK-LABEL: @test2(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %rhs = add i32 %a, 1
   %and = and i32 %a, %rhs
@@ -21,9 +36,24 @@ define i1 @test2(i32 %a) {
   ret i1 %res
 }
 
+define i1 @test2v(<2 x i32> %a) {
+; CHECK-LABEL: @test2v(
+; CHECK-NEXT:    [[RHS:%.*]] = add <2 x i32> [[A:%.*]], <i32 0, i32 1>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A]], [[RHS]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 1
+; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[EXT]], 1
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %rhs = add <2 x i32> %a, <i32 0, i32 1>
+  %and = and <2 x i32> %a, %rhs
+  %ext = extractelement <2 x i32> %and, i32 1
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}
+
 define i1 @test3(i32 %a) {
 ; CHECK-LABEL: @test3(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %rhs = add i32 %a, 7
   %and = and i32 %a, %rhs
@@ -31,13 +61,28 @@ define i1 @test3(i32 %a) {
   ret i1 %res
 }
 
+define i1 @test3v(<2 x i32> %a) {
+; CHECK-LABEL: @test3v(
+; CHECK-NEXT:    [[RHS:%.*]] = add <2 x i32> [[A:%.*]], <i32 7, i32 0>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A]], [[RHS]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 0
+; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[EXT]], 1
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %rhs = add <2 x i32> %a, <i32 7, i32 0>
+  %and = and <2 x i32> %a, %rhs
+  %ext = extractelement <2 x i32> %and, i32 0
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}
+
 @B = external global i32
 declare void @llvm.assume(i1)
 
 ; Known bits without a constant
 define i1 @test4(i32 %a) {
 ; CHECK-LABEL: @test4(
-; CHECK:         [[B:%.*]] = load i32, i32* @B
+; CHECK-NEXT:    [[B:%.*]] = load i32, i32* @B
 ; CHECK-NEXT:    [[B_AND:%.*]] = and i32 [[B]], 1
 ; CHECK-NEXT:    [[B_CND:%.*]] = icmp eq i32 [[B_AND]], 1
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[B_CND]])
@@ -57,8 +102,8 @@ define i1 @test4(i32 %a) {
 ; Negative test - even number
 define i1 @test5(i32 %a) {
 ; CHECK-LABEL: @test5(
-; CHECK:         [[RHS:%.*]] = add i32 %a, 2
-; CHECK-NEXT:    [[AND:%.*]] = and i32 %a, [[RHS]]
+; CHECK-NEXT:    [[RHS:%.*]] = add i32 [[A:%.*]], 2
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[A]], [[RHS]]
 ; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[AND]], 1
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
@@ -68,12 +113,42 @@ define i1 @test5(i32 %a) {
   ret i1 %res
 }
 
+define i1 @test5v(<2 x i32> %a) {
+; CHECK-LABEL: @test5v(
+; CHECK-NEXT:    [[RHS:%.*]] = add <2 x i32> [[A:%.*]], <i32 2, i32 0>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A]], [[RHS]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 1
+; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[EXT]], 1
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %rhs = add <2 x i32> %a, <i32 2, i32 0>
+  %and = and <2 x i32> %a, %rhs
+  %ext = extractelement <2 x i32> %and, i32 1
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}
+
 define i1 @test6(i32 %a) {
 ; CHECK-LABEL: @test6(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %lhs = add i32 %a, -1
   %and = and i32 %lhs, %a
   %res = icmp eq i32 %and, 1
   ret i1 %res
 }
+
+define i1 @test6v(<2 x i32> %a) {
+; CHECK-LABEL: @test6v(
+; CHECK-NEXT:    [[LHS:%.*]] = add <2 x i32> [[A:%.*]], <i32 0, i32 -1>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[LHS]], [[A]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 1
+; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[EXT]], 1
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %lhs = add <2 x i32> %a, <i32 0, i32 -1>
+  %and = and <2 x i32> %lhs, %a
+  %ext = extractelement <2 x i32> %and, i32 1
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}