[llvm] e225e77 - [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.

[via llvm-commits]

Author: lewis-revill
Date: 2020-03-18T19:52:23Z
New Revision: e225e770f7e94cc1b6e2fababcc7b238db65cfee

URL: https://github.com/llvm/llvm-project/commit/e225e770f7e94cc1b6e2fababcc7b238db65cfee
DIFF: https://github.com/llvm/llvm-project/commit/e225e770f7e94cc1b6e2fababcc7b238db65cfee.diff

LOG: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.

This patch rewrites the RegisterBankEmitter class to derive
RegisterClassHierarchy from CodeGenTarget::getRegBank() rather than
constructing our own copy. All are now accessed through a const
reference.

Differential Revision: https://reviews.llvm.org/D76006

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenRegisters.cpp
    llvm/utils/TableGen/CodeGenRegisters.h
    llvm/utils/TableGen/RegisterBankEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index bebee0d685d7..4584bc7cfae3 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1275,8 +1275,8 @@ CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
   return &RegClasses.back();
 }
 
-CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
-  if (CodeGenRegisterClass *RC = Def2RC[Def])
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
+  if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
     return RC;
 
   PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");

diff  --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index f15138b04b01..2b200adef312 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -719,7 +719,7 @@ namespace llvm {
     }
 
     // Find a register class from its def.
-    CodeGenRegisterClass *getRegClass(Record*);
+    CodeGenRegisterClass *getRegClass(const Record *) const;
 
     /// getRegisterClassForRegister - Find the register class that contains the
     /// specified physical register.  If the register is not in a register

diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 7f6b3931d3de..586f857b1fb0 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -19,6 +19,7 @@
 
 #include "CodeGenHwModes.h"
 #include "CodeGenRegisters.h"
+#include "CodeGenTarget.h"
 
 #define DEBUG_TYPE "register-bank-emitter"
 
@@ -60,10 +61,10 @@ class RegisterBank {
 
   /// Get the register classes listed in the RegisterBank.RegisterClasses field.
   std::vector<const CodeGenRegisterClass *>
-  getExplictlySpecifiedRegisterClasses(
-      CodeGenRegBank &RegisterClassHierarchy) const {
+  getExplicitlySpecifiedRegisterClasses(
+      const CodeGenRegBank &RegisterClassHierarchy) const {
     std::vector<const CodeGenRegisterClass *> RCs;
-    for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
+    for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
     return RCs;
   }
@@ -104,8 +105,8 @@ class RegisterBank {
 
 class RegisterBankEmitter {
 private:
+  CodeGenTarget Target;
   RecordKeeper &Records;
-  CodeGenRegBank RegisterClassHierarchy;
 
   void emitHeader(raw_ostream &OS, const StringRef TargetName,
                   const std::vector<RegisterBank> &Banks);
@@ -115,8 +116,7 @@ class RegisterBankEmitter {
                                    std::vector<RegisterBank> &Banks);
 
 public:
-  RegisterBankEmitter(RecordKeeper &R)
-      : Records(R), RegisterClassHierarchy(Records, CodeGenHwModes(R)) {}
+  RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
 
   void run(raw_ostream &OS);
 };
@@ -167,8 +167,8 @@ void RegisterBankEmitter::emitBaseClassDefinition(
 ///                multiple times for a given class if there are multiple paths
 ///                to the class.
 static void visitRegisterBankClasses(
-    CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
-    const Twine Kind,
+    const CodeGenRegBank &RegisterClassHierarchy,
+    const CodeGenRegisterClass *RC, const Twine Kind,
     std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
     SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
 
@@ -212,6 +212,7 @@ static void visitRegisterBankClasses(
 void RegisterBankEmitter::emitBaseClassImplementation(
     raw_ostream &OS, StringRef TargetName,
     std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
 
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n";
@@ -275,10 +276,8 @@ void RegisterBankEmitter::emitBaseClassImplementation(
 }
 
 void RegisterBankEmitter::run(raw_ostream &OS) {
-  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
-  if (Targets.size() != 1)
-    PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
-  StringRef TargetName = Targets[0]->getName();
+  StringRef TargetName = Target.getName();
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
 
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
@@ -286,7 +285,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
     RegisterBank Bank(*V);
 
     for (const CodeGenRegisterClass *RC :
-         Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
       visitRegisterBankClasses(
           RegisterClassHierarchy, RC, "explicit",
           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
@@ -301,14 +300,14 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
   }
 
   // Warn about ambiguous MIR caused by register bank/class name clashes.
-  for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
+  for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
     for (const auto &Bank : Banks) {
-      if (Bank.getName().lower() == Class->getName().lower()) {
+      if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
         PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
                                              "distinct from register classes "
                                              "to avoid ambiguous MIR");
         PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
-        PrintNote(Class->getLoc(), "RegisterClass was declared here");
+        PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");
       }
     }
   }