[llvm] d000655 - [Alignment][NFC] Deprecate getMaxAlignment
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 18 06:53:44 PDT 2020
Just wondering, how does deprecation help?
Since bots use -Werror, if there's uses of the deprecated methods within LLVM,
this will break the build, and if there aren't any uses, then it's dead code
that can be freely dropped under guarantee of the lack of C++
interface stability..
Roman
On Wed, Mar 18, 2020 at 4:49 PM Guillaume Chatelet via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
>
> Author: Guillaume Chatelet
> Date: 2020-03-18T14:48:45+01:00
> New Revision: d000655a8cd58c8449a86a1761038c8c1dd78d87
>
> URL: https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87
> DIFF: https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87.diff
>
> LOG: [Alignment][NFC] Deprecate getMaxAlignment
>
> Summary:
> This is patch is part of a series to introduce an Alignment type.
> See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
> See this patch for the introduction of the type: https://reviews.llvm.org/D64790
>
> Reviewers: courbet
>
> Subscribers: jholewinski, arsenm, dschuff, jyknight, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits
>
> Tags: #llvm
>
> Differential Revision: https://reviews.llvm.org/D76348
>
> Added:
>
>
> Modified:
> llvm/include/llvm/CodeGen/MachineFrameInfo.h
> llvm/lib/CodeGen/MIRPrinter.cpp
> llvm/lib/CodeGen/TargetRegisterInfo.cpp
> llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
> llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
> llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
> llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> llvm/lib/Target/ARM/ARMFrameLowering.cpp
> llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
> llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
> llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
> llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
> llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
> llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
> llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
> llvm/lib/Target/Sparc/SparcFrameLowering.cpp
> llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
> llvm/lib/Target/X86/X86FrameLowering.cpp
>
> Removed:
>
>
>
> ################################################################################
> diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
> index 681a27b0ad29..384b206fc220 100644
> --- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h
> +++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
> @@ -583,7 +583,10 @@ class MachineFrameInfo {
>
> /// Return the alignment in bytes that this function must be aligned to,
> /// which is greater than the default stack alignment provided by the target.
> - unsigned getMaxAlignment() const { return MaxAlignment.value(); }
> + LLVM_ATTRIBUTE_DEPRECATED(unsigned getMaxAlignment() const,
> + "Use getMaxAlign instead") {
> + return MaxAlignment.value();
> + }
> /// Return the alignment in bytes that this function must be aligned to,
> /// which is greater than the default stack alignment provided by the target.
> Align getMaxAlign() const { return MaxAlignment; }
>
> diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
> index 1fb557e4dfcd..2a150b1368df 100644
> --- a/llvm/lib/CodeGen/MIRPrinter.cpp
> +++ b/llvm/lib/CodeGen/MIRPrinter.cpp
> @@ -334,7 +334,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
> YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
> YamlMFI.StackSize = MFI.getStackSize();
> YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
> - YamlMFI.MaxAlignment = MFI.getMaxAlignment();
> + YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
> YamlMFI.AdjustsStack = MFI.adjustsStack();
> YamlMFI.HasCalls = MFI.hasCalls();
> YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
>
> diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
> index 1c582ff06560..34d1f7e611ab 100644
> --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
> +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
> @@ -468,8 +468,8 @@ bool TargetRegisterInfo::needsStackRealignment(
> const MachineFrameInfo &MFI = MF.getFrameInfo();
> const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
> const Function &F = MF.getFunction();
> - unsigned StackAlign = TFI->getStackAlignment();
> - bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
> + Align StackAlign = TFI->getStackAlign();
> + bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) ||
> F.hasFnAttribute(Attribute::StackAlignment));
> if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
> if (canRealignStack(MF))
>
> diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
> index 91a8bca99397..9f17d7d0762b 100644
> --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
> @@ -1217,8 +1217,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
> false, NeedsWinCFI, &HasWinCFI);
>
> if (NeedsRealignment) {
> - const unsigned Alignment = MFI.getMaxAlignment();
> - const unsigned NrBitsToZero = countTrailingZeros(Alignment);
> + const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
> assert(NrBitsToZero > 1);
> assert(scratchSPReg != AArch64::SP);
>
>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
> index 1a56f382ca80..733db1eae80d 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
> +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
> @@ -631,8 +631,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
> Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
> Info.PrivateSegmentSize = FrameInfo.getStackSize();
> if (MFI->isStackRealigned())
> - Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
> -
> + Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
>
> Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
> MRI.isPhysRegUsed(AMDGPU::VCC_HI);
>
> diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
> index d0c713d07d87..60b35981de9c 100644
> --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
> +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
> @@ -768,7 +768,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
>
> if (TRI.needsStackRealignment(MF)) {
> HasFP = true;
> - const unsigned Alignment = MFI.getMaxAlignment();
> + const unsigned Alignment = MFI.getMaxAlign().value();
>
> RoundedSize += Alignment;
> if (LiveRegs.empty()) {
> @@ -834,8 +834,9 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
>
> const MachineFrameInfo &MFI = MF.getFrameInfo();
> uint32_t NumBytes = MFI.getStackSize();
> - uint32_t RoundedSize = FuncInfo->isStackRealigned() ?
> - NumBytes + MFI.getMaxAlignment() : NumBytes;
> + uint32_t RoundedSize = FuncInfo->isStackRealigned()
> + ? NumBytes + MFI.getMaxAlign().value()
> + : NumBytes;
>
> if (RoundedSize != 0 && hasFP(MF)) {
> const unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
>
> diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> index 4dcb1f62577a..9fc566761c5c 100644
> --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> @@ -1360,17 +1360,18 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
> // If there's dynamic realignment, adjust for it.
> if (RI.needsStackRealignment(MF)) {
> MachineFrameInfo &MFI = MF.getFrameInfo();
> - unsigned MaxAlign = MFI.getMaxAlignment();
> + Align MaxAlign = MFI.getMaxAlign();
> assert (!AFI->isThumb1OnlyFunction());
> // Emit bic r6, r6, MaxAlign
> - assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
> - "immediates larger than 256 with all lower "
> - "bits set.");
> + assert(MaxAlign <= Align(256) &&
> + "The BIC instruction cannot encode "
> + "immediates larger than 256 with all lower "
> + "bits set.");
> unsigned bicOpc = AFI->isThumbFunction() ?
> ARM::t2BICri : ARM::BICri;
> BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
> .addReg(ARM::R6, RegState::Kill)
> - .addImm(MaxAlign - 1)
> + .addImm(MaxAlign.value() - 1)
> .add(predOps(ARMCC::AL))
> .add(condCodeOp());
> }
>
> diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
> index 9807971b558b..8910b66c235e 100644
> --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
> +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
> @@ -260,13 +260,13 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
> MachineBasicBlock &MBB,
> MachineBasicBlock::iterator MBBI,
> const DebugLoc &DL, const unsigned Reg,
> - const unsigned Alignment,
> + const Align Alignment,
> const bool MustBeSingleInstruction) {
> const ARMSubtarget &AST =
> static_cast<const ARMSubtarget &>(MF.getSubtarget());
> const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
> - const unsigned AlignMask = Alignment - 1;
> - const unsigned NrBitsToZero = countTrailingZeros(Alignment);
> + const unsigned AlignMask = Alignment.value() - 1U;
> + const unsigned NrBitsToZero = Log2(Alignment);
> assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
> if (!AFI->isThumbFunction()) {
> // if the BFC instruction is available, use that to zero the lower
> @@ -346,7 +346,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
> assert(!AFI->isThumb1OnlyFunction() &&
> "This emitPrologue does not support Thumb1!");
> bool isARM = !AFI->isThumbFunction();
> - unsigned Align = STI.getFrameLowering()->getStackAlignment();
> + Align Alignment = STI.getFrameLowering()->getStackAlign();
> unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
> unsigned NumBytes = MFI.getStackSize();
> const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
> @@ -437,8 +437,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
> // Determine starting offsets of spill areas.
> unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
> unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
> - unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
> - unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
> + Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4);
> + unsigned DPRGapSize =
> + (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign.value();
> unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
> int FramePtrOffsetInPush = 0;
> if (HasFP) {
> @@ -696,7 +697,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
> // If aligned NEON registers were spilled, the stack has already been
> // realigned.
> if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
> - unsigned MaxAlign = MFI.getMaxAlignment();
> + Align MaxAlign = MFI.getMaxAlign();
> assert(!AFI->isThumb1OnlyFunction());
> if (!AFI->isThumbFunction()) {
> emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
> @@ -1168,7 +1169,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
> int FI = CSI[i].getFrameIdx();
> // The even-numbered registers will be 16-byte aligned, the odd-numbered
> // registers will be 8-byte aligned.
> - MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
> + MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));
>
> // The stack slot for D8 needs to be maximally aligned because this is
> // actually the point where we align the stack pointer. MachineFrameInfo
> @@ -1177,7 +1178,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
> // over-alignment is not realized because the code inserted below adjusts
> // the stack pointer by numregs * 8 before aligning the stack pointer.
> if (DNum == 0)
> - MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
> + MFI.setObjectAlignment(FI, MFI.getMaxAlign());
> }
>
> // Move the stack pointer to the d8 spill slot, and align it at the same
> @@ -1200,7 +1201,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
> .add(predOps(ARMCC::AL))
> .add(condCodeOp());
>
> - unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
> + Align MaxAlign = MF.getFrameInfo().getMaxAlign();
> // We must set parameter MustBeSingleInstruction to true, since
> // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
> // stack alignment. Luckily, this can always be done since all ARM
>
> diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
> index c0632016ccf0..c017ebb885da 100644
> --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
> +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
> @@ -402,7 +402,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
> AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
>
> if (RegInfo->needsStackRealignment(MF)) {
> - const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
> + const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
> // Emit the following sequence, using R4 as a temporary, since we cannot use
> // SP as a source or destination register for the shifts:
> // mov r4, sp
>
> diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
> index 1a2d92719c5e..1601d5600cc2 100644
> --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
> +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
> @@ -591,7 +591,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
> auto &HII = *HST.getInstrInfo();
> auto &HRI = *HST.getRegisterInfo();
>
> - unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
> + Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
>
> // Calculate the total stack frame size.
> // Get the number of bytes to allocate from the FrameInfo.
> @@ -603,7 +603,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
> FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
> MFI.setStackSize(FrameSize);
>
> - bool AlignStack = (MaxAlign > getStackAlignment());
> + bool AlignStack = (MaxAlign > getStackAlign());
>
> // Get the number of bytes to allocate from the FrameInfo.
> unsigned NumBytes = MFI.getStackSize();
> @@ -742,7 +742,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
> if (AlignStack) {
> BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
> .addReg(SP)
> - .addImm(-int64_t(MaxAlign));
> + .addImm(-int64_t(MaxAlign.value()));
> }
> // If the stack-checking is enabled, and we spilled the callee-saved
> // registers inline (i.e. did not use a spill function), then call
> @@ -1507,7 +1507,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
> // via AP, which may not be available at the particular place in the program.
> MachineFrameInfo &MFI = MF.getFrameInfo();
> bool HasAlloca = MFI.hasVarSizedObjects();
> - bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
> + bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
>
> if (!HasAlloca || !NeedsAlign)
> return;
>
> diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> index e220a0765e2d..388c5feb0e11 100644
> --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> @@ -734,8 +734,8 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
> MachineFrameInfo &MFI = MF->getFrameInfo();
> const HexagonFrameLowering *HFI = HST->getFrameLowering();
> int FX = cast<FrameIndexSDNode>(N)->getIndex();
> - unsigned StkA = HFI->getStackAlignment();
> - unsigned MaxA = MFI.getMaxAlignment();
> + Align StkA = HFI->getStackAlign();
> + Align MaxA = MFI.getMaxAlign();
> SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
> SDLoc DL(N);
> SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
> @@ -1284,9 +1284,9 @@ void HexagonDAGToDAGISel::emitFunctionEntryCode() {
> MachineFrameInfo &MFI = MF->getFrameInfo();
> MachineBasicBlock *EntryBB = &MF->front();
> unsigned AR = FuncInfo->CreateReg(MVT::i32);
> - unsigned EntryMaxA = MFI.getMaxAlignment();
> + Align EntryMaxA = MFI.getMaxAlign();
> BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
> - .addImm(EntryMaxA);
> + .addImm(EntryMaxA.value());
> MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
> }
>
> @@ -1296,7 +1296,7 @@ void HexagonDAGToDAGISel::updateAligna() {
> return;
> auto *AlignaI = const_cast<MachineInstr*>(HFI.getAlignaInstr(*MF));
> assert(AlignaI != nullptr);
> - unsigned MaxA = MF->getFrameInfo().getMaxAlignment();
> + unsigned MaxA = MF->getFrameInfo().getMaxAlign().value();
> if (AlignaI->getOperand(1).getImm() < MaxA)
> AlignaI->getOperand(1).setImm(MaxA);
> }
>
> diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
> index eddc2b8e61f7..3c84ed057fd1 100644
> --- a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
> +++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
> @@ -32,8 +32,8 @@ void LanaiFrameLowering::determineFrameLayout(MachineFunction &MF) const {
> unsigned FrameSize = MFI.getStackSize();
>
> // Get the alignment.
> - unsigned StackAlign = LRI->needsStackRealignment(MF) ? MFI.getMaxAlignment()
> - : getStackAlignment();
> + Align StackAlign =
> + LRI->needsStackRealignment(MF) ? MFI.getMaxAlign() : getStackAlign();
>
> // Get the maximum call frame size of all the calls.
> unsigned MaxCallFrameSize = MFI.getMaxCallFrameSize();
>
> diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
> index d5a44801dcf2..e0f4f9eab9da 100644
> --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
> +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
> @@ -539,11 +539,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
> // addiu $Reg, $zero, -MaxAlignment
> // andi $sp, $sp, $Reg
> Register VR = MF.getRegInfo().createVirtualRegister(RC);
> - assert(isInt<16>(MFI.getMaxAlignment()) &&
> + assert((Log2(MFI.getMaxAlign()) < 16) &&
> "Function's alignment size requirement is not supported.");
> - int MaxAlign = -(int)MFI.getMaxAlignment();
> + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value();
>
> - BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
> + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign);
> BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
>
> if (hasBP(MF)) {
>
> diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> index 76fe78ee0bfb..6fcadfb5a160 100644
> --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> @@ -1634,8 +1634,8 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters(
> const MachineFrameInfo &MFI = MF.getFrameInfo();
> int NumBytes = (int) MFI.getStackSize();
> if (NumBytes) {
> - O << "\t.local .align " << MFI.getMaxAlignment() << " .b8 \t" << DEPOTNAME
> - << getFunctionNumber() << "[" << NumBytes << "];\n";
> + O << "\t.local .align " << MFI.getMaxAlign().value() << " .b8 \t"
> + << DEPOTNAME << getFunctionNumber() << "[" << NumBytes << "];\n";
> if (static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit()) {
> O << "\t.reg .b64 \t%SP;\n";
> O << "\t.reg .b64 \t%SPL;\n";
>
> diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
> index 4b91ca8368db..93695a854c24 100644
> --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
> +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
> @@ -437,9 +437,9 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
> UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
>
> // Get stack alignments. The frame must be aligned to the greatest of these:
> - unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
> - unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
> - unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
> + Align TargetAlign = getStackAlign(); // alignment required per the ABI
> + Align MaxAlign = MFI.getMaxAlign(); // algmt required by data in frame
> + Align Alignment = std::max(TargetAlign, MaxAlign);
>
> const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
>
> @@ -471,7 +471,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
> // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
> // that allocations will be aligned.
> if (MFI.hasVarSizedObjects())
> - maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
> + maxCallFrameSize = alignTo(maxCallFrameSize, Alignment);
>
> // Update the new max call frame size if the caller passes in a valid pointer.
> if (NewMaxCallFrameSize)
> @@ -481,7 +481,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
> FrameSize += maxCallFrameSize;
>
> // Make sure the frame is aligned.
> - FrameSize = (FrameSize + AlignMask) & ~AlignMask;
> + FrameSize = alignTo(FrameSize, Alignment);
>
> return FrameSize;
> }
> @@ -667,7 +667,7 @@ PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
> int NegFrameSize = -FrameSize;
> bool IsLargeFrame = !isInt<16>(NegFrameSize);
> MachineFrameInfo &MFI = MF.getFrameInfo();
> - unsigned MaxAlign = MFI.getMaxAlignment();
> + Align MaxAlign = MFI.getMaxAlign();
> bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
>
> return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
> @@ -867,10 +867,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
> }
>
> // Get stack alignments.
> - unsigned MaxAlign = MFI.getMaxAlignment();
> + Align MaxAlign = MFI.getMaxAlign();
> if (HasBP && MaxAlign > 1)
> - assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
> - "Invalid alignment!");
> + assert(Log2(MaxAlign) < 16 && "Invalid alignment!");
>
> // Frames of 32KB & larger require special handling because they cannot be
> // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
> @@ -1007,15 +1006,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
> if (HasBP && MaxAlign > 1) {
> if (isPPC64)
> BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
> - .addReg(SPReg)
> - .addImm(0)
> - .addImm(64 - Log2_32(MaxAlign));
> + .addReg(SPReg)
> + .addImm(0)
> + .addImm(64 - Log2(MaxAlign));
> else // PPC32...
> BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
> - .addReg(SPReg)
> - .addImm(0)
> - .addImm(32 - Log2_32(MaxAlign))
> - .addImm(31);
> + .addReg(SPReg)
> + .addImm(0)
> + .addImm(32 - Log2(MaxAlign))
> + .addImm(31);
> if (!isLargeFrame) {
> BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
> .addReg(ScratchReg, RegState::Kill)
> @@ -2058,8 +2057,8 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
> RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
>
> // Might we have over-aligned allocas?
> - bool HasAlVars = MFI.hasVarSizedObjects() &&
> - MFI.getMaxAlignment() > getStackAlignment();
> + bool HasAlVars =
> + MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();
>
> // These kinds of spills might need two registers.
> if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
>
> diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
> index caa9d7b6b869..35d3c420c3c3 100644
> --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
> +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
> @@ -499,7 +499,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
> // Get stack alignments.
> const PPCFrameLowering *TFI = getFrameLowering(MF);
> unsigned TargetAlign = TFI->getStackAlignment();
> - unsigned MaxAlign = MFI.getMaxAlignment();
> + unsigned MaxAlign = MFI.getMaxAlign().value();
> assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
> "Maximum call-frame size not sufficiently aligned");
>
>
> diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
> index 072f0d902cc3..927e8534ece8 100644
> --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
> +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
> @@ -142,10 +142,10 @@ void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
> uint64_t FrameSize = MFI.getStackSize();
>
> // Get the alignment.
> - unsigned StackAlign = getStackAlignment();
> + Align StackAlign = getStackAlign();
> if (RI->needsStackRealignment(MF)) {
> - unsigned MaxStackAlign = std::max(StackAlign, MFI.getMaxAlignment());
> - FrameSize += (MaxStackAlign - StackAlign);
> + Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
> + FrameSize += (MaxStackAlign.value() - StackAlign.value());
> StackAlign = MaxStackAlign;
> }
>
> @@ -359,15 +359,15 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
> // Realign Stack
> const RISCVRegisterInfo *RI = STI.getRegisterInfo();
> if (RI->needsStackRealignment(MF)) {
> - unsigned MaxAlignment = MFI.getMaxAlignment();
> + Align MaxAlignment = MFI.getMaxAlign();
>
> const RISCVInstrInfo *TII = STI.getInstrInfo();
> - if (isInt<12>(-(int)MaxAlignment)) {
> + if (isInt<12>(-(int)MaxAlignment.value())) {
> BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
> .addReg(SPReg)
> - .addImm(-(int)MaxAlignment);
> + .addImm(-(int)MaxAlignment.value());
> } else {
> - unsigned ShiftAmount = countTrailingZeros(MaxAlignment);
> + unsigned ShiftAmount = Log2(MaxAlignment);
> Register VR =
> MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
> BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
>
> diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
> index 0f74f2bb344c..6bb3a51df0c3 100644
> --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
> +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
> @@ -104,7 +104,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
> // rather than reporting an error, as would be sensible. This is
> // poor, but fixing that bogosity is going to be a large project.
> // For now, just see if it's lied, and report an error here.
> - if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
> + if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())
> report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
> "stack re-alignment, but LLVM couldn't handle it "
> "(probably because it has a dynamic alloca).");
> @@ -146,9 +146,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
>
> // Finally, ensure that the size is sufficiently aligned for the
> // data on the stack.
> - if (MFI.getMaxAlignment() > 0) {
> - NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
> - }
> + NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
>
> // Update stack size with corrected value.
> MFI.setStackSize(NumBytes);
> @@ -189,9 +187,10 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
> regUnbiased = SP::O6;
>
> // andn %regUnbiased, MaxAlign-1, %regUnbiased
> - int MaxAlign = MFI.getMaxAlignment();
> + Align MaxAlign = MFI.getMaxAlign();
> BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
> - .addReg(regUnbiased).addImm(MaxAlign - 1);
> + .addReg(regUnbiased)
> + .addImm(MaxAlign.value() - 1U);
>
> if (Bias) {
> // add %g1, -BIAS, %o6
>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
> index 21b81d8cd0ed..036c2aee0050 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
> @@ -201,11 +201,9 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,
> }
> if (HasBP) {
> Register BitmaskReg = MRI.createVirtualRegister(PtrRC);
> - unsigned Alignment = MFI.getMaxAlignment();
> - assert((1u << countTrailingZeros(Alignment)) == Alignment &&
> - "Alignment must be a power of 2");
> + Align Alignment = MFI.getMaxAlign();
> BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg)
> - .addImm((int)~(Alignment - 1));
> + .addImm((int)~(Alignment.value() - 1));
> BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32),
> WebAssembly::SP32)
> .addReg(WebAssembly::SP32)
>
> diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
> index 9d7d5b7a6f18..1661497849d1 100644
> --- a/llvm/lib/Target/X86/X86FrameLowering.cpp
> +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
> @@ -1042,15 +1042,15 @@ static unsigned calculateSetFPREG(uint64_t SPAdjust) {
> // go with the minimum SlotSize.
> uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
> const MachineFrameInfo &MFI = MF.getFrameInfo();
> - uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
> - unsigned StackAlign = getStackAlignment();
> + Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
> + Align StackAlign = getStackAlign();
> if (MF.getFunction().hasFnAttribute("stackrealign")) {
> if (MFI.hasCalls())
> MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
> else if (MaxAlign < SlotSize)
> - MaxAlign = SlotSize;
> + MaxAlign = Align(SlotSize);
> }
> - return MaxAlign;
> + return MaxAlign.value();
> }
>
> void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
>
>
>
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