[PATCH] D76356: [AMDGPU] Introduce more scratch registers in the ABI.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added reviewers: arsenm, t-tye, rampitec.
Herald added subscribers: llvm-commits, kerbowa, arphaman, hiraditya, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.
Herald added a project: LLVM.

The AMDGPU target has a convention which defined all VGPRs
(execept the initial 32 argument registers) as callee-saves.
This convention is not efficient always, esp. when the callee
requiring more registers, ended up emitting a higher number of
spills, even though its caller requires only a few.

This patch revises the ABI by introducing more scratch registers
which a callee is free to use.
The 256 vgpr registers now become:

  32 - argument registers
  96 - scratch registers
  128 - callee save registers.

The scratch registers and the CSRs are intermixed at regular
intervals to obtain a better occupancy. Also, a cost model is
applied to these registers so that RA balances out the allocation
of the VPGRs without much fragmenting the VGPR blocks.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76356

Files:
  llvm/docs/AMDGPUUsage.rst
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
  llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/nested-calls.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
  llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
  llvm/test/CodeGen/AMDGPU/wave32.ll

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