[PATCH] D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, lenary, luismarques, simoncook, apazos, weiwei, shiva0217.
Herald added subscribers: llvm-commits, evandro, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, kito-cheng, niosHD, sabuasal, johnrusso, rbar, hiraditya, rovka.
Herald added a project: LLVM.
lewis-revill updated this revision to Diff 251036.
lewis-revill added a comment.

Fix copy/paste mistakes in check lines


This patch defines ALU operations with XLen types as legal. Necessary pathways for lowering sign extend and zero extend operations are defined as legal too.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76354

Files:
  llvm/lib/Target/RISCV/RISCVLegalizerInfo.cpp
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/alu64.mir

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