[PATCH] D76292: [ARM] Change VDUP type to i32 for MVE

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samparker, efriedma, simon_tatham, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.

The MVE VDUP instruction take a GPR and splats into every lane of a vector register. Unlike NEON we do not have a VDUPLANE equivalent instruction. Previously a VDUP to a v4f32/v8f16 would be represented as a (v4f32 VDUP f32:$x), which would mean the instruction pattern needs to add a COPY_TO_REGCLASS to the GPR.

Instead this now converts that earlier during an ISel DAG combine, converting (VDUP x) to (VDUP (bitcast x)). This can allow instruction selection to tell that the pattern needs to be an i32, which in one of the testcases allows it to use ldr (or specifically ldm) over (vldr;vmov).

Whilst being simple enough for floats, I cannot see a target independent BITCAST equivalent for getting a half into a i32. This uses a VMOVrh ARMISD node, which doesn't know the same tricks.


https://reviews.llvm.org/D76292

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fmas.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/dup.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll
  llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll

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