[PATCH] D73666: AMDGPU/GlobalISel: Adjust image load register type based on dmask

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle accepted this revision.
nhaehnle added a comment.
This revision is now accepted and ready to land.

Minor comments inline, LGTM apart from that.



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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3254
 
-    SmallVector<Register, 5> UnmergeResults(TFETy.getNumElements(), Dst1Reg);
-    int NumDataElts = TFETy.getNumElements() - 1;
+  // FIXME: Do we need to notify the observer of the instruction change?
+  MI.getOperand(0).setReg(NewResultReg);
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nhaehnle wrote:
> You do now have an Observer argument here, right?
I'm assuming this will be addressed by the scoped observer exit introduced with the previous commit. Please remember to remove the comment.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3268
+    // TODO: Make sure the TFE operand bit is set.
+    // FIXME: Do we need to notify the observer of the instruction change?
+    MI.RemoveOperand(1);
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As above: please remember to remove the comment.


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