[PATCH] D75944: [x86][seses] Don't LFENCE data invariant insts

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp:129
+      // data invariant instructions, then continue to the next instruction.
+      if (!LFENCEDataInvariantInstructions &&
+          (TII->isDataInvariant(MI) || TII->isDataInvariantLoad(MI))) {
----------------
zbrid wrote:
> craig.topper wrote:
> > Don't the instructions that match isDataInvariantLoad still pull things into the cache?
> This may be true. I don't know. Data invariant instructions were supposed to be a stand in for a more specific "instructions that don't release info to side channels" and perhaps that's a very different thing. I think someone with better expertise than I have would need to evaluate whether this is a secure flag to set.
I think this was only meant to capture instructions whose execution latency doesn't vary based on the data value. For example divide by a power of 2 takes a different number of cycles than division by other values.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75944/new/

https://reviews.llvm.org/D75944