[PATCH] D76201: [TargetLowering] Only demand a rotation's modulo amount bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 250587.
RKSimon added a comment.

Added explicit masking to AVX rotation lowering.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76201/new/

https://reviews.llvm.org/D76201

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/PowerPC/rotl-2.ll
  llvm/test/CodeGen/SystemZ/rot-01.ll
  llvm/test/CodeGen/SystemZ/rot-02.ll
  llvm/test/CodeGen/SystemZ/shift-04.ll
  llvm/test/CodeGen/SystemZ/shift-08.ll
  llvm/test/CodeGen/Thumb2/thumb2-ror.ll
  llvm/test/CodeGen/X86/combine-rotates.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll

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