[PATCH] D76209: [llvm][SVE] Addressing mode for FF/NF loads.

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4488
+/// integers MVT::nx<M>xi<bits> such that M x bits = 128.
+static EVT getSVEPackedVectorTypeFromEC(LLVMContext &Ctx, ElementCount EC) {
+  assert(EC.Scalable && "Expecting scalable Element Count.");
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Is this change needed here?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4498
 /// Root. If such EVT cannot be retrived, it returns an invalid EVT.
 static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
   if (isa<MemSDNode>(Root))
----------------
Why do you have to update this method? I've tried to find the relation with other changes in this file and I failed :)


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1550
               (I PPR:$gp, GPR64sp:$base, (i64 0))>;
+
   }
----------------
[Nit] - unrelated


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll:379
+
+define <vscale x 2 x double> @ldff1d_f64(<vscale x 2 x i1> %pg, double* %a, i64 %offset) {
 ; CHECK-LABEL: ldff1d_f64:
----------------
FIXME


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76209/new/

https://reviews.llvm.org/D76209