[llvm] 3ffb5ef - [PowerPC] Regenerate rotate tests

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 15 11:29:23 PDT 2020


Author: Simon Pilgrim
Date: 2020-03-15T18:29:00Z
New Revision: 3ffb5ef7b030b239df74e9885d96634ba7df92eb

URL: https://github.com/llvm/llvm-project/commit/3ffb5ef7b030b239df74e9885d96634ba7df92eb
DIFF: https://github.com/llvm/llvm-project/commit/3ffb5ef7b030b239df74e9885d96634ba7df92eb.diff

LOG: [PowerPC] Regenerate rotate tests

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/rotl-2.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/rotl-2.ll b/llvm/test/CodeGen/PowerPC/rotl-2.ll
index 43d34f6f8c73..1b24b878e713 100644
--- a/llvm/test/CodeGen/PowerPC/rotl-2.ll
+++ b/llvm/test/CodeGen/PowerPC/rotl-2.ll
@@ -1,9 +1,12 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep rotlwi | count 2
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep clrlwi | count 2
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep rotlw | count 4
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | not grep or
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s
 
 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
+; CHECK-LABEL: rotl32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi 4, 4, 24
+; CHECK-NEXT:    rotlw 3, 3, 4
+; CHECK-NEXT:    blr
 	%shift.upgrd.1 = zext i8 %Amt to i32		; <i32> [#uses=1]
 	%B = shl i32 %A, %shift.upgrd.1		; <i32> [#uses=1]
 	%Amt2 = sub i8 32, %Amt		; <i8> [#uses=1]
@@ -14,6 +17,12 @@ define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
 }
 
 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
+; CHECK-LABEL: rotr32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subfic 4, 4, 32
+; CHECK-NEXT:    clrlwi 4, 4, 24
+; CHECK-NEXT:    rotlw 3, 3, 4
+; CHECK-NEXT:    blr
 	%shift.upgrd.3 = zext i8 %Amt to i32		; <i32> [#uses=1]
 	%B = lshr i32 %A, %shift.upgrd.3		; <i32> [#uses=1]
 	%Amt2 = sub i8 32, %Amt		; <i8> [#uses=1]
@@ -24,6 +33,10 @@ define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
 }
 
 define i32 @rotli32(i32 %A) nounwind {
+; CHECK-LABEL: rotli32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rotlwi 3, 3, 5
+; CHECK-NEXT:    blr
 	%B = shl i32 %A, 5		; <i32> [#uses=1]
 	%C = lshr i32 %A, 27		; <i32> [#uses=1]
 	%D = or i32 %B, %C		; <i32> [#uses=1]
@@ -31,6 +44,10 @@ define i32 @rotli32(i32 %A) nounwind {
 }
 
 define i32 @rotri32(i32 %A) nounwind {
+; CHECK-LABEL: rotri32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rotlwi 3, 3, 27
+; CHECK-NEXT:    blr
 	%B = lshr i32 %A, 5		; <i32> [#uses=1]
 	%C = shl i32 %A, 27		; <i32> [#uses=1]
 	%D = or i32 %B, %C		; <i32> [#uses=1]


        


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