[llvm] 775bf62 - [SystemZ] Regenerate rotate/shift tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 15 09:43:16 PDT 2020
Author: Simon Pilgrim
Date: 2020-03-15T16:42:46Z
New Revision: 775bf626982dc8b22e92af244fd58962a651c4dc
URL: https://github.com/llvm/llvm-project/commit/775bf626982dc8b22e92af244fd58962a651c4dc
DIFF: https://github.com/llvm/llvm-project/commit/775bf626982dc8b22e92af244fd58962a651c4dc.diff
LOG: [SystemZ] Regenerate rotate/shift tests
Added:
Modified:
llvm/test/CodeGen/SystemZ/rot-01.ll
llvm/test/CodeGen/SystemZ/rot-02.ll
llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
llvm/test/CodeGen/SystemZ/shift-01.ll
llvm/test/CodeGen/SystemZ/shift-02.ll
llvm/test/CodeGen/SystemZ/shift-03.ll
llvm/test/CodeGen/SystemZ/shift-04.ll
llvm/test/CodeGen/SystemZ/shift-05.ll
llvm/test/CodeGen/SystemZ/shift-06.ll
llvm/test/CodeGen/SystemZ/shift-07.ll
llvm/test/CodeGen/SystemZ/shift-08.ll
llvm/test/CodeGen/SystemZ/shift-09.ll
llvm/test/CodeGen/SystemZ/shift-10.ll
llvm/test/CodeGen/SystemZ/shift-11.ll
llvm/test/CodeGen/SystemZ/shift-12.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/SystemZ/rot-01.ll b/llvm/test/CodeGen/SystemZ/rot-01.ll
index ea275e68df54..fc1608d1b546 100644
--- a/llvm/test/CodeGen/SystemZ/rot-01.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test shortening of NILL to NILF when the result is used as a rotate amount.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,10 @@
; Test 32-bit rotate.
define i32 @f1(i32 %val, i32 %amt) {
; CHECK-LABEL: f1:
-; CHECK: nill %r3, 31
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%mod = urem i32 %amt, 32
%inv = sub i32 32, %mod
@@ -21,8 +24,10 @@ define i32 @f1(i32 %val, i32 %amt) {
; Test 64-bit rotate.
define i64 @f2(i64 %val, i64 %amt) {
; CHECK-LABEL: f2:
-; CHECK: nill %r3, 31
-; CHECK: rllg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%mod = urem i64 %amt, 32
%inv = sub i64 64, %mod
diff --git a/llvm/test/CodeGen/SystemZ/rot-02.ll b/llvm/test/CodeGen/SystemZ/rot-02.ll
index 12b09f131850..68f5620122c6 100644
--- a/llvm/test/CodeGen/SystemZ/rot-02.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test removal of AND operations that don't affect last 6 bits of rotate amount
; operand.
;
@@ -6,8 +7,10 @@
; Test that AND is not removed when some lower 6 bits are not set.
define i32 @f1(i32 %val, i32 %amt) {
; CHECK-LABEL: f1:
-; CHECK: nil{{[lf]}} %r3, 31
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %amt, 31
%inv = sub i32 32, %and
@@ -22,8 +25,9 @@ define i32 @f1(i32 %val, i32 %amt) {
; Test removal of AND mask with only bottom 6 bits set.
define i32 @f2(i32 %val, i32 %amt) {
; CHECK-LABEL: f2:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %amt, 63
%inv = sub i32 32, %and
@@ -38,8 +42,9 @@ define i32 @f2(i32 %val, i32 %amt) {
; Test removal of AND mask including but not limited to bottom 6 bits.
define i32 @f3(i32 %val, i32 %amt) {
; CHECK-LABEL: f3:
-; CHECK-NOT: nil{{[lf]}} %r3, 255
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %amt, 255
%inv = sub i32 32, %and
@@ -54,8 +59,9 @@ define i32 @f3(i32 %val, i32 %amt) {
; Test removal of AND mask from RLLG.
define i64 @f4(i64 %val, i64 %amt) {
; CHECK-LABEL: f4:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: rllg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %amt, 63
%inv = sub i64 64, %and
@@ -70,9 +76,11 @@ define i64 @f4(i64 %val, i64 %amt) {
; Test that AND is not entirely removed if the result is reused.
define i32 @f5(i32 %val, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: nil{{[lf]}} %r3, 63
-; CHECK: ar %r2, %r3
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: nilf %r3, 63
+; CHECK-NEXT: ar %r2, %r3
+; CHECK-NEXT: br %r14
%and = and i32 %amt, 63
%inv = sub i32 32, %and
diff --git a/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll b/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
index c29f6ab996c6..29adcf6b5a11 100644
--- a/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test that the case of (64 - shift) used by a shift/rotate instruction is
; implemented with an lcr. This should also work for any multiple of 64.
;
@@ -5,8 +6,10 @@
define i64 @f1(i64 %in, i64 %sh) {
; CHECK-LABEL: f1:
-; CHECK: lcr %r1, %r3
-; CHECK: sllg %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 64, %sh
%shl = shl i64 %in, %sub
ret i64 %shl
@@ -14,8 +17,10 @@ define i64 @f1(i64 %in, i64 %sh) {
define i64 @f2(i64 %in, i64 %sh) {
; CHECK-LABEL: f2:
-; CHECK: lcr %r1, %r3
-; CHECK: srag %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: srag %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 64, %sh
%shl = ashr i64 %in, %sub
ret i64 %shl
@@ -23,8 +28,10 @@ define i64 @f2(i64 %in, i64 %sh) {
define i64 @f3(i64 %in, i64 %sh) {
; CHECK-LABEL: f3:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 64, %sh
%shl = lshr i64 %in, %sub
ret i64 %shl
@@ -32,8 +39,10 @@ define i64 @f3(i64 %in, i64 %sh) {
define i64 @f4(i64 %in, i64 %sh) {
; CHECK-LABEL: f4:
-; CHECK: lcr %r1, %r3
-; CHECK: rllg %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: rllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%shr = lshr i64 %in, %sh
%sub = sub i64 64, %sh
%shl = shl i64 %in, %sub
@@ -43,8 +52,10 @@ define i64 @f4(i64 %in, i64 %sh) {
define i64 @f5(i64 %in, i64 %sh) {
; CHECK-LABEL: f5:
-; CHECK: lcr %r1, %r3
-; CHECK: sllg %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 128, %sh
%shl = shl i64 %in, %sub
ret i64 %shl
@@ -52,8 +63,10 @@ define i64 @f5(i64 %in, i64 %sh) {
define i64 @f6(i64 %in, i64 %sh) {
; CHECK-LABEL: f6:
-; CHECK: lcr %r1, %r3
-; CHECK: srag %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: srag %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 256, %sh
%shl = ashr i64 %in, %sub
ret i64 %shl
@@ -61,8 +74,10 @@ define i64 @f6(i64 %in, i64 %sh) {
define i64 @f7(i64 %in, i64 %sh) {
; CHECK-LABEL: f7:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r2, %r2, 0(%r1)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%sub = sub i64 512, %sh
%shl = lshr i64 %in, %sub
ret i64 %shl
@@ -70,10 +85,12 @@ define i64 @f7(i64 %in, i64 %sh) {
define i64 @f8(i64 %in, i64 %sh) {
; CHECK-LABEL: f8:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r0, %r2, 0(%r3)
-; CHECK: sllg %r2, %r2, 0(%r1)
-; CHECK: ogr %r2, %r0
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcr %r1, %r3
+; CHECK-NEXT: srlg %r0, %r2, 0(%r3)
+; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: ogr %r2, %r0
+; CHECK-NEXT: br %r14
%shr = lshr i64 %in, %sh
%sub = sub i64 1024, %sh
%shl = shl i64 %in, %sub
diff --git a/llvm/test/CodeGen/SystemZ/shift-01.ll b/llvm/test/CodeGen/SystemZ/shift-01.ll
index 924c62383287..9c1142d633aa 100644
--- a/llvm/test/CodeGen/SystemZ/shift-01.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit shifts left.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SLL range.
define i32 @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: sll %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 1
+; CHECK-NEXT: br %r14
%shift = shl i32 %a, 1
ret i32 %shift
}
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
; Check the high end of the defined SLL range.
define i32 @f2(i32 %a) {
; CHECK-LABEL: f2:
-; CHECK: sll %r2, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 31
+; CHECK-NEXT: br %r14
%shift = shl i32 %a, 31
ret i32 %shift
}
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: sll %r2, 32
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = shl i32 %a, 32
ret i32 %shift
}
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
; CHECK-LABEL: f4:
-; CHECK-NOT: sll %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, -1
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i32 %amt, 1
%shift = shl i32 %a, %sub
ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: sll %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = shl i32 %a, %amt
ret i32 %shift
}
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: sll %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%shift = shl i32 %a, %add
ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
; CHECK-LABEL: f7:
-; CHECK: sll %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%trunc = trunc i64 %add to i32
%shift = shl i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
; CHECK-LABEL: f8:
-; CHECK: sll %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 4095(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4095
%shift = shl i32 %a, %add
ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: sll %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, 4096
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4096
%shift = shl i32 %a, %add
ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: sll %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ar %r3, %r4
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %b, %c
%shift = shl i32 %a, %add
ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: sll %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 0(%r3)
+; CHECK-NEXT: sll %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i32, i32 *%ptr
%shift = shl i32 %a, %amt
ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-02.ll b/llvm/test/CodeGen/SystemZ/shift-02.ll
index e9cbb2b1a8f8..cf3e69d556d5 100644
--- a/llvm/test/CodeGen/SystemZ/shift-02.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit logical shifts right.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SRL range.
define i32 @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: srl %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 1
+; CHECK-NEXT: br %r14
%shift = lshr i32 %a, 1
ret i32 %shift
}
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
; Check the high end of the defined SRL range.
define i32 @f2(i32 %a) {
; CHECK-LABEL: f2:
-; CHECK: srl %r2, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 31
+; CHECK-NEXT: br %r14
%shift = lshr i32 %a, 31
ret i32 %shift
}
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: srl %r2, 32
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = lshr i32 %a, 32
ret i32 %shift
}
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
; CHECK-LABEL: f4:
-; CHECK-NOT: srl %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, -1
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i32 %amt, 1
%shift = lshr i32 %a, %sub
ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: srl %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = lshr i32 %a, %amt
ret i32 %shift
}
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: srl %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%shift = lshr i32 %a, %add
ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
; CHECK-LABEL: f7:
-; CHECK: srl %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%trunc = trunc i64 %add to i32
%shift = lshr i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
; CHECK-LABEL: f8:
-; CHECK: srl %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 4095(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4095
%shift = lshr i32 %a, %add
ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: srl %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, 4096
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4096
%shift = lshr i32 %a, %add
ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: srl %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ar %r3, %r4
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %b, %c
%shift = lshr i32 %a, %add
ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: srl %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 0(%r3)
+; CHECK-NEXT: srl %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i32, i32 *%ptr
%shift = lshr i32 %a, %amt
ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-03.ll b/llvm/test/CodeGen/SystemZ/shift-03.ll
index 13cdbb0ea5fa..e5a95f9707b5 100644
--- a/llvm/test/CodeGen/SystemZ/shift-03.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit arithmetic shifts right.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SRA range.
define i32 @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: sra %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 1
+; CHECK-NEXT: br %r14
%shift = ashr i32 %a, 1
ret i32 %shift
}
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
; Check the high end of the defined SRA range.
define i32 @f2(i32 %a) {
; CHECK-LABEL: f2:
-; CHECK: sra %r2, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 31
+; CHECK-NEXT: br %r14
%shift = ashr i32 %a, 31
ret i32 %shift
}
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: sra %r2, 32
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = ashr i32 %a, 32
ret i32 %shift
}
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
; CHECK-LABEL: f4:
-; CHECK-NOT: sra %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, -1
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i32 %amt, 1
%shift = ashr i32 %a, %sub
ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: sra %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = ashr i32 %a, %amt
ret i32 %shift
}
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: sra %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%shift = ashr i32 %a, %add
ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
; CHECK-LABEL: f7:
-; CHECK: sra %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%trunc = trunc i64 %add to i32
%shift = ashr i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
; CHECK-LABEL: f8:
-; CHECK: sra %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 4095(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4095
%shift = ashr i32 %a, %add
ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: sra %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ahi %r3, 4096
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 4096
%shift = ashr i32 %a, %add
ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: sra %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ar %r3, %r4
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %b, %c
%shift = ashr i32 %a, %add
ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: sra %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 0(%r3)
+; CHECK-NEXT: sra %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i32, i32 *%ptr
%shift = ashr i32 %a, %amt
ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-04.ll b/llvm/test/CodeGen/SystemZ/shift-04.ll
index bdabc54322ad..0b9309be3538 100644
--- a/llvm/test/CodeGen/SystemZ/shift-04.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit rotates left.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the RLL range.
define i32 @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: rll %r2, %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 1
+; CHECK-NEXT: br %r14
%parta = shl i32 %a, 1
%partb = lshr i32 %a, 31
%or = or i32 %parta, %partb
@@ -16,8 +18,9 @@ define i32 @f1(i32 %a) {
; Check the high end of the defined RLL range.
define i32 @f2(i32 %a) {
; CHECK-LABEL: f2:
-; CHECK: rll %r2, %r2, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 31
+; CHECK-NEXT: br %r14
%parta = shl i32 %a, 31
%partb = lshr i32 %a, 1
%or = or i32 %parta, %partb
@@ -27,8 +30,9 @@ define i32 @f2(i32 %a) {
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: rll
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lhi %r2, -1
+; CHECK-NEXT: br %r14
%parta = shl i32 %a, 32
%partb = lshr i32 %a, 0
%or = or i32 %parta, %partb
@@ -38,8 +42,9 @@ define i32 @f3(i32 %a) {
; Check variable shifts.
define i32 @f4(i32 %a, i32 %amt) {
; CHECK-LABEL: f4:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%amtb = sub i32 32, %amt
%parta = shl i32 %a, %amt
%partb = lshr i32 %a, %amtb
@@ -50,8 +55,9 @@ define i32 @f4(i32 %a, i32 %amt) {
; Check shift amounts that have a constant term.
define i32 @f5(i32 %a, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%sub = sub i32 32, %add
%parta = shl i32 %a, %add
@@ -63,8 +69,9 @@ define i32 @f5(i32 %a, i32 %amt) {
; ...and again with a truncated 64-bit shift amount.
define i32 @f6(i32 %a, i64 %amt) {
; CHECK-LABEL: f6:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%addtrunc = trunc i64 %add to i32
%sub = sub i32 32, %addtrunc
@@ -77,8 +84,9 @@ define i32 @f6(i32 %a, i64 %amt) {
; ...and again with a
diff erent truncation representation.
define i32 @f7(i32 %a, i64 %amt) {
; CHECK-LABEL: f7:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%sub = sub i64 32, %add
%addtrunc = trunc i64 %add to i32
@@ -93,8 +101,9 @@ define i32 @f7(i32 %a, i64 %amt) {
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
; CHECK-LABEL: f8:
-; CHECK: rll %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 524287(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 524287
%sub = sub i32 32, %add
%parta = shl i32 %a, %add
@@ -107,9 +116,10 @@ define i32 @f8(i32 %a, i32 %amt) {
; addition.
define i32 @f9(i32 %a, i32 %amt) {
; CHECK-LABEL: f9:
-; CHECK: afi %r3, 524288
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, 524288
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 524288
%sub = sub i32 32, %add
%parta = shl i32 %a, %add
@@ -121,8 +131,9 @@ define i32 @f9(i32 %a, i32 %amt) {
; Check cases where 1 is subtracted from the shift amount.
define i32 @f10(i32 %a, i32 %amt) {
; CHECK-LABEL: f10:
-; CHECK: rll %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, -1(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i32 %amt, 1
%subb = sub i32 32, %suba
%parta = shl i32 %a, %suba
@@ -135,8 +146,9 @@ define i32 @f10(i32 %a, i32 %amt) {
; Again, we could mask the shift amount instead.
define i32 @f11(i32 %a, i32 %amt) {
; CHECK-LABEL: f11:
-; CHECK: rll %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, -524288(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i32 %amt, 524288
%subb = sub i32 32, %suba
%parta = shl i32 %a, %suba
@@ -149,9 +161,10 @@ define i32 @f11(i32 %a, i32 %amt) {
; addition.
define i32 @f12(i32 %a, i32 %amt) {
; CHECK-LABEL: f12:
-; CHECK: afi %r3, -524289
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, -524289
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i32 %amt, 524289
%subb = sub i32 32, %suba
%parta = shl i32 %a, %suba
@@ -163,9 +176,10 @@ define i32 @f12(i32 %a, i32 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i32 @f13(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f13:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: rll %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ar %r3, %r4
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %b, %c
%sub = sub i32 32, %add
%parta = shl i32 %a, %add
@@ -177,9 +191,10 @@ define i32 @f13(i32 %a, i32 %b, i32 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f14(i32 %a, i32 *%ptr) {
; CHECK-LABEL: f14:
-; CHECK: l %r1, 0(%r3)
-; CHECK: rll %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 0(%r3)
+; CHECK-NEXT: rll %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i32, i32 *%ptr
%amtb = sub i32 32, %amt
%parta = shl i32 %a, %amt
@@ -192,8 +207,9 @@ define i32 @f14(i32 %a, i32 *%ptr) {
; instcombine.
define i32 @f15(i32 %a, i32 %amt) {
; CHECK-LABEL: f15:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%sub = sub i32 22, %amt
%parta = shl i32 %a, %add
@@ -205,8 +221,9 @@ define i32 @f15(i32 %a, i32 %amt) {
; Likewise for f7.
define i32 @f16(i32 %a, i64 %amt) {
; CHECK-LABEL: f16:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%sub = sub i64 22, %amt
%addtrunc = trunc i64 %add to i32
@@ -220,8 +237,9 @@ define i32 @f16(i32 %a, i64 %amt) {
; Check cases where (-x & 31) is used instead of 32 - x.
define i32 @f17(i32 %x, i32 %y) {
; CHECK-LABEL: f17:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
entry:
%shl = shl i32 %x, %y
%sub = sub i32 0, %y
@@ -234,8 +252,9 @@ entry:
; ...and again with ((32 - x) & 31).
define i32 @f18(i32 %x, i32 %y) {
; CHECK-LABEL: f18:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
entry:
%shl = shl i32 %x, %y
%sub = sub i32 32, %y
@@ -248,8 +267,15 @@ entry:
; This is not a rotation.
define i32 @f19(i32 %x, i32 %y) {
; CHECK-LABEL: f19:
-; CHECK-NOT: rll
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lr %r0, %r2
+; CHECK-NEXT: sll %r0, 0(%r3)
+; CHECK-NEXT: lhi %r1, 16
+; CHECK-NEXT: sr %r1, %r3
+; CHECK-NEXT: nill %r1, 31
+; CHECK-NEXT: srl %r2, 0(%r1)
+; CHECK-NEXT: or %r2, %r0
+; CHECK-NEXT: br %r14
entry:
%shl = shl i32 %x, %y
%sub = sub i32 16, %y
@@ -262,8 +288,9 @@ entry:
; Repeat f17 with an addition on the shift count.
define i32 @f20(i32 %x, i32 %y) {
; CHECK-LABEL: f20:
-; CHECK: rll %r2, %r2, 199(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rll %r2, %r2, 199(%r3)
+; CHECK-NEXT: br %r14
entry:
%add = add i32 %y, 199
%shl = shl i32 %x, %add
@@ -277,8 +304,9 @@ entry:
; ...and again with the InstCombine version.
define i32 @f21(i32 %x, i32 %y) {
; CHECK-LABEL: f21:
-; CHECK: rll %r2, %r2, 199(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rll %r2, %r2, 199(%r3)
+; CHECK-NEXT: br %r14
entry:
%add = add i32 %y, 199
%shl = shl i32 %x, %add
diff --git a/llvm/test/CodeGen/SystemZ/shift-05.ll b/llvm/test/CodeGen/SystemZ/shift-05.ll
index 625ec9b0b92c..f1062aca3574 100644
--- a/llvm/test/CodeGen/SystemZ/shift-05.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit shifts left.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SLLG range.
define i64 @f1(i64 %a) {
; CHECK-LABEL: f1:
-; CHECK: sllg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 1
+; CHECK-NEXT: br %r14
%shift = shl i64 %a, 1
ret i64 %shift
}
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
; Check the high end of the defined SLLG range.
define i64 @f2(i64 %a) {
; CHECK-LABEL: f2:
-; CHECK: sllg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 63
+; CHECK-NEXT: br %r14
%shift = shl i64 %a, 63
ret i64 %shift
}
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: sllg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = shl i64 %a, 64
ret i64 %shift
}
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
; CHECK-LABEL: f4:
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = shl i64 %a, %amt
ret i64 %shift
}
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
; CHECK-LABEL: f5:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%shift = shl i64 %a, %add
ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = sext i32 %add to i64
%shift = shl i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
; CHECK-LABEL: f7:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = zext i32 %add to i64
%shift = shl i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
; CHECK-LABEL: f8:
-; CHECK: sllg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 524287(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524287
%shift = shl i64 %a, %add
ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
; addition.
define i64 @f9(i64 %a, i64 %amt) {
; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, 524288
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524288
%shift = shl i64 %a, %add
ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
; CHECK-LABEL: f10:
-; CHECK: sllg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, -1(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 1
%shift = shl i64 %a, %sub
ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
; CHECK-LABEL: f11:
-; CHECK: sllg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, -524288(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524288
%shift = shl i64 %a, %sub
ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
; addition.
define i64 @f12(i64 %a, i64 %amt) {
; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, -524289
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524289
%shift = shl i64 %a, %sub
ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: sllg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r3, %r4
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %b, %c
%shift = shl i64 %a, %add
ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: sllg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 4(%r3)
+; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i64, i64 *%ptr
%shift = shl i64 %a, %amt
ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-06.ll b/llvm/test/CodeGen/SystemZ/shift-06.ll
index 6769fbb4343e..e956e6293f48 100644
--- a/llvm/test/CodeGen/SystemZ/shift-06.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-06.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit logical shifts right.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SRLG range.
define i64 @f1(i64 %a) {
; CHECK-LABEL: f1:
-; CHECK: srlg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 1
+; CHECK-NEXT: br %r14
%shift = lshr i64 %a, 1
ret i64 %shift
}
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
; Check the high end of the defined SRLG range.
define i64 @f2(i64 %a) {
; CHECK-LABEL: f2:
-; CHECK: srlg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 63
+; CHECK-NEXT: br %r14
%shift = lshr i64 %a, 63
ret i64 %shift
}
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: srlg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = lshr i64 %a, 64
ret i64 %shift
}
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
; CHECK-LABEL: f4:
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = lshr i64 %a, %amt
ret i64 %shift
}
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
; CHECK-LABEL: f5:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%shift = lshr i64 %a, %add
ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = sext i32 %add to i64
%shift = lshr i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
; CHECK-LABEL: f7:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = zext i32 %add to i64
%shift = lshr i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
; CHECK-LABEL: f8:
-; CHECK: srlg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 524287(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524287
%shift = lshr i64 %a, %add
ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
; addition.
define i64 @f9(i64 %a, i64 %amt) {
; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, 524288
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524288
%shift = lshr i64 %a, %add
ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
; CHECK-LABEL: f10:
-; CHECK: srlg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, -1(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 1
%shift = lshr i64 %a, %sub
ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
; CHECK-LABEL: f11:
-; CHECK: srlg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, -524288(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524288
%shift = lshr i64 %a, %sub
ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
; addition.
define i64 @f12(i64 %a, i64 %amt) {
; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, -524289
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524289
%shift = lshr i64 %a, %sub
ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: srlg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r3, %r4
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %b, %c
%shift = lshr i64 %a, %add
ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: srlg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 4(%r3)
+; CHECK-NEXT: srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i64, i64 *%ptr
%shift = lshr i64 %a, %amt
ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-07.ll b/llvm/test/CodeGen/SystemZ/shift-07.ll
index e0a11f6e6ed1..fb2712d084b7 100644
--- a/llvm/test/CodeGen/SystemZ/shift-07.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit arithmetic shifts right.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the SRAG range.
define i64 @f1(i64 %a) {
; CHECK-LABEL: f1:
-; CHECK: srag %r2, %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 1
+; CHECK-NEXT: br %r14
%shift = ashr i64 %a, 1
ret i64 %shift
}
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
; Check the high end of the defined SRAG range.
define i64 @f2(i64 %a) {
; CHECK-LABEL: f2:
-; CHECK: srag %r2, %r2, 63
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 63
+; CHECK-NEXT: br %r14
%shift = ashr i64 %a, 63
ret i64 %shift
}
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: srag
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%shift = ashr i64 %a, 64
ret i64 %shift
}
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
; CHECK-LABEL: f4:
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%shift = ashr i64 %a, %amt
ret i64 %shift
}
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
; CHECK-LABEL: f5:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%shift = ashr i64 %a, %add
ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = sext i32 %add to i64
%shift = ashr i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
; CHECK-LABEL: f7:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%addext = zext i32 %add to i64
%shift = ashr i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
; CHECK-LABEL: f8:
-; CHECK: srag %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 524287(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524287
%shift = ashr i64 %a, %add
ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
; addition.
define i64 @f9(i64 %a, i64 %amt) {
; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, 524288
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524288
%shift = ashr i64 %a, %add
ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
; CHECK-LABEL: f10:
-; CHECK: srag %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, -1(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 1
%shift = ashr i64 %a, %sub
ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
; CHECK-LABEL: f11:
-; CHECK: srag %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, -524288(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524288
%shift = ashr i64 %a, %sub
ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
; addition.
define i64 @f12(i64 %a, i64 %amt) {
; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, -524289
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%sub = sub i64 %amt, 524289
%shift = ashr i64 %a, %sub
ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: srag %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r3, %r4
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %b, %c
%shift = ashr i64 %a, %add
ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: srag %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 4(%r3)
+; CHECK-NEXT: srag %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i64, i64 *%ptr
%shift = ashr i64 %a, %amt
ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-08.ll b/llvm/test/CodeGen/SystemZ/shift-08.ll
index 027b05f73134..8d98602d8768 100644
--- a/llvm/test/CodeGen/SystemZ/shift-08.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-08.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit rotates left.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
; Check the low end of the RLLG range.
define i64 @f1(i64 %a) {
; CHECK-LABEL: f1:
-; CHECK: rllg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 1
+; CHECK-NEXT: br %r14
%parta = shl i64 %a, 1
%partb = lshr i64 %a, 63
%or = or i64 %parta, %partb
@@ -16,8 +18,9 @@ define i64 @f1(i64 %a) {
; Check the high end of the defined RLLG range.
define i64 @f2(i64 %a) {
; CHECK-LABEL: f2:
-; CHECK: rllg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 63
+; CHECK-NEXT: br %r14
%parta = shl i64 %a, 63
%partb = lshr i64 %a, 1
%or = or i64 %parta, %partb
@@ -27,8 +30,9 @@ define i64 @f2(i64 %a) {
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
; CHECK-LABEL: f3:
-; CHECK-NOT: rllg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lghi %r2, -1
+; CHECK-NEXT: br %r14
%parta = shl i64 %a, 64
%partb = lshr i64 %a, 0
%or = or i64 %parta, %partb
@@ -38,8 +42,9 @@ define i64 @f3(i64 %a) {
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
; CHECK-LABEL: f4:
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%amtb = sub i64 64, %amt
%parta = shl i64 %a, %amt
%partb = lshr i64 %a, %amtb
@@ -50,8 +55,9 @@ define i64 @f4(i64 %a, i64 %amt) {
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
; CHECK-LABEL: f5:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 10
%sub = sub i64 64, %add
%parta = shl i64 %a, %add
@@ -63,8 +69,9 @@ define i64 @f5(i64 %a, i64 %amt) {
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%sub = sub i32 64, %add
%addext = sext i32 %add to i64
@@ -78,8 +85,9 @@ define i64 @f6(i64 %a, i32 %amt) {
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
; CHECK-LABEL: f7:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 10
%sub = sub i32 64, %add
%addext = zext i32 %add to i64
@@ -94,8 +102,9 @@ define i64 @f7(i64 %a, i32 %amt) {
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
; CHECK-LABEL: f8:
-; CHECK: rllg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, 524287(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524287
%sub = sub i64 64, %add
%parta = shl i64 %a, %add
@@ -108,9 +117,10 @@ define i64 @f8(i64 %a, i64 %amt) {
; addition.
define i64 @f9(i64 %a, i64 %amt) {
; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, 524288
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %amt, 524288
%sub = sub i64 64, %add
%parta = shl i64 %a, %add
@@ -122,8 +132,9 @@ define i64 @f9(i64 %a, i64 %amt) {
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
; CHECK-LABEL: f10:
-; CHECK: rllg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, -1(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i64 %amt, 1
%subb = sub i64 64, %suba
%parta = shl i64 %a, %suba
@@ -136,8 +147,9 @@ define i64 @f10(i64 %a, i64 %amt) {
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
; CHECK-LABEL: f11:
-; CHECK: rllg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rllg %r2, %r2, -524288(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i64 %amt, 524288
%subb = sub i64 64, %suba
%parta = shl i64 %a, %suba
@@ -150,9 +162,10 @@ define i64 @f11(i64 %a, i64 %amt) {
; addition.
define i64 @f12(i64 %a, i64 %amt) {
; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: afi %r3, -524289
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%suba = sub i64 %amt, 524289
%subb = sub i64 64, %suba
%parta = shl i64 %a, %suba
@@ -164,9 +177,10 @@ define i64 @f12(i64 %a, i64 %amt) {
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: rllg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r3, %r4
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%add = add i64 %b, %c
%sub = sub i64 64, %add
%parta = shl i64 %a, %add
@@ -178,9 +192,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: rllg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r1, 4(%r3)
+; CHECK-NEXT: rllg %r2, %r2, 0(%r1)
+; CHECK-NEXT: br %r14
%amt = load i64, i64 *%ptr
%amtb = sub i64 64, %amt
%parta = shl i64 %a, %amt
diff --git a/llvm/test/CodeGen/SystemZ/shift-09.ll b/llvm/test/CodeGen/SystemZ/shift-09.ll
index c87cf0d9a1ee..0822c7a44bf2 100644
--- a/llvm/test/CodeGen/SystemZ/shift-09.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-09.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test three-operand shifts.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -5,8 +6,9 @@
; Check that we use SLLK over SLL where useful.
define i32 @f1(i32 %a, i32 %b, i32 %amt) {
; CHECK-LABEL: f1:
-; CHECK: sllk %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllk %r2, %r3, 15(%r4)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = shl i32 %b, %add
ret i32 %shift
@@ -15,8 +17,9 @@ define i32 @f1(i32 %a, i32 %b, i32 %amt) {
; Check that we use SLL over SLLK where possible.
define i32 @f2(i32 %a, i32 %amt) {
; CHECK-LABEL: f2:
-; CHECK: sll %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 15(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = shl i32 %a, %add
ret i32 %shift
@@ -25,8 +28,9 @@ define i32 @f2(i32 %a, i32 %amt) {
; Check that we use SRLK over SRL where useful.
define i32 @f3(i32 %a, i32 %b, i32 %amt) {
; CHECK-LABEL: f3:
-; CHECK: srlk %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlk %r2, %r3, 15(%r4)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = lshr i32 %b, %add
ret i32 %shift
@@ -35,8 +39,9 @@ define i32 @f3(i32 %a, i32 %b, i32 %amt) {
; Check that we use SRL over SRLK where possible.
define i32 @f4(i32 %a, i32 %amt) {
; CHECK-LABEL: f4:
-; CHECK: srl %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 15(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = lshr i32 %a, %add
ret i32 %shift
@@ -45,8 +50,9 @@ define i32 @f4(i32 %a, i32 %amt) {
; Check that we use SRAK over SRA where useful.
define i32 @f5(i32 %a, i32 %b, i32 %amt) {
; CHECK-LABEL: f5:
-; CHECK: srak %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srak %r2, %r3, 15(%r4)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = ashr i32 %b, %add
ret i32 %shift
@@ -55,8 +61,9 @@ define i32 @f5(i32 %a, i32 %b, i32 %amt) {
; Check that we use SRA over SRAK where possible.
define i32 @f6(i32 %a, i32 %amt) {
; CHECK-LABEL: f6:
-; CHECK: sra %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 15(%r3)
+; CHECK-NEXT: br %r14
%add = add i32 %amt, 15
%shift = ashr i32 %a, %add
ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-10.ll b/llvm/test/CodeGen/SystemZ/shift-10.ll
index 176f7dea8c35..711ec5d38eb8 100644
--- a/llvm/test/CodeGen/SystemZ/shift-10.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-10.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test compound shifts.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,9 +6,11 @@
; Test a shift right followed by a sign extension. This can use two shifts.
define i64 @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: risbg %r0, %r2, 63, 191, 63
-; CHECK: lcgr %r2, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r0, %r2, 63, 191, 63
+; CHECK-NEXT: lcgr %r2, %r0
+; CHECK-NEXT: br %r14
%shr = lshr i32 %a, 1
%trunc = trunc i32 %shr to i1
%ext = sext i1 %trunc to i64
@@ -18,9 +21,11 @@ define i64 @f1(i32 %a) {
; ashr/sext pair.
define i64 @f2(i32 %a) {
; CHECK-LABEL: f2:
-; CHECK: risbg %r0, %r2, 63, 191, 34
-; CHECK: lcgr %r2, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r0, %r2, 63, 191, 34
+; CHECK-NEXT: lcgr %r2, %r0
+; CHECK-NEXT: br %r14
%shr = lshr i32 %a, 30
%trunc = trunc i32 %shr to i1
%ext = sext i1 %trunc to i64
@@ -31,8 +36,10 @@ define i64 @f2(i32 %a) {
; is possible.
define i64 @f3(i32 %a) {
; CHECK-LABEL: f3:
-; CHECK: risbg %r2, %r2, 27, 181, 9
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 27, 181, 9
+; CHECK-NEXT: br %r14
%shr = lshr i32 %a, 1
%ext = zext i32 %shr to i64
%shl = shl i64 %ext, 10
@@ -43,8 +50,10 @@ define i64 @f3(i32 %a) {
; ...and again with a larger right shift.
define i64 @f4(i32 %a) {
; CHECK-LABEL: f4:
-; CHECK: risbg %r2, %r2, 30, 158, 3
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 30, 158, 3
+; CHECK-NEXT: br %r14
%shr = lshr i32 %a, 30
%ext = sext i32 %shr to i64
%shl = shl i64 %ext, 33
@@ -56,9 +65,11 @@ define i64 @f4(i32 %a) {
; bottom 3 matter.
define i64 @f5(i32 %a) {
; CHECK-LABEL: f5:
-; CHECK: risbg %r2, %r2, 29, 158, 3
-; CHECK: lhi %r2, 7
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 29, 158, 3
+; CHECK-NEXT: lhi %r2, 7
+; CHECK-NEXT: br %r14
%shr = lshr i32 %a, 30
%ext = sext i32 %shr to i64
%shl = shl i64 %ext, 33
@@ -70,8 +81,9 @@ define i64 @f5(i32 %a) {
; that matters.
define i64 @f6(i64 %a) {
; CHECK-LABEL: f6:
-; CHECK: risbg %r2, %r2, 55, 183, 19
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 55, 183, 19
+; CHECK-NEXT: br %r14
%shl = shl i64 %a, 10
%shr = ashr i64 %shl, 60
%and = and i64 %shr, 256
@@ -81,9 +93,11 @@ define i64 @f6(i64 %a) {
; Test another form of f1.
define i64 @f7(i32 %a) {
; CHECK-LABEL: f7:
-; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
-; CHECK: srag %r2, [[REG]], 63
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: sllg %r0, %r2, 62
+; CHECK-NEXT: srag %r2, %r0, 63
+; CHECK-NEXT: br %r14
%1 = shl i32 %a, 30
%sext = ashr i32 %1, 31
%ext = sext i32 %sext to i64
diff --git a/llvm/test/CodeGen/SystemZ/shift-11.ll b/llvm/test/CodeGen/SystemZ/shift-11.ll
index 3d6fc6a05143..fab9fde9d6d7 100644
--- a/llvm/test/CodeGen/SystemZ/shift-11.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-11.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test shortening of NILL to NILF when the result is used as a shift amount.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,10 @@
; Test logical shift right.
define i32 @f1(i32 %a, i32 %sh) {
; CHECK-LABEL: f1:
-; CHECK: nill %r3, 31
-; CHECK: srl %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 31
%shift = lshr i32 %a, %and
ret i32 %shift
@@ -15,8 +18,10 @@ define i32 @f1(i32 %a, i32 %sh) {
; Test arithmetic shift right.
define i32 @f2(i32 %a, i32 %sh) {
; CHECK-LABEL: f2:
-; CHECK: nill %r3, 31
-; CHECK: sra %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 31
%shift = ashr i32 %a, %and
ret i32 %shift
@@ -25,8 +30,10 @@ define i32 @f2(i32 %a, i32 %sh) {
; Test shift left.
define i32 @f3(i32 %a, i32 %sh) {
; CHECK-LABEL: f3:
-; CHECK: nill %r3, 31
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 31
%shift = shl i32 %a, %and
ret i32 %shift
@@ -35,8 +42,10 @@ define i32 @f3(i32 %a, i32 %sh) {
; Test 64-bit logical shift right.
define i64 @f4(i64 %a, i64 %sh) {
; CHECK-LABEL: f4:
-; CHECK: nill %r3, 31
-; CHECK: srlg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 31
%shift = lshr i64 %a, %and
ret i64 %shift
@@ -45,8 +54,10 @@ define i64 @f4(i64 %a, i64 %sh) {
; Test 64-bit arithmetic shift right.
define i64 @f5(i64 %a, i64 %sh) {
; CHECK-LABEL: f5:
-; CHECK: nill %r3, 31
-; CHECK: srag %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 31
%shift = ashr i64 %a, %and
ret i64 %shift
@@ -55,8 +66,10 @@ define i64 @f5(i64 %a, i64 %sh) {
; Test 64-bit shift left.
define i64 @f6(i64 %a, i64 %sh) {
; CHECK-LABEL: f6:
-; CHECK: nill %r3, 31
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 31
%shift = shl i64 %a, %and
ret i64 %shift
@@ -65,8 +78,10 @@ define i64 @f6(i64 %a, i64 %sh) {
; Test shift with negative 32-bit value.
define i32 @f8(i32 %a, i32 %sh, i32 %test) {
; CHECK-LABEL: f8:
-; CHECK: nill %r3, 65529
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 65529
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, -7
%shift = shl i32 %a, %and
@@ -76,8 +91,10 @@ define i32 @f8(i32 %a, i32 %sh, i32 %test) {
; Test shift with negative 64-bit value.
define i64 @f9(i64 %a, i64 %sh, i64 %test) {
; CHECK-LABEL: f9:
-; CHECK: nill %r3, 65529
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 65529
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, -7
%shift = shl i64 %a, %and
diff --git a/llvm/test/CodeGen/SystemZ/shift-12.ll b/llvm/test/CodeGen/SystemZ/shift-12.ll
index 53d3d5362dfd..7559602aa256 100644
--- a/llvm/test/CodeGen/SystemZ/shift-12.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-12.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test removal of AND operations that don't affect last 6 bits of shift amount
; operand.
;
@@ -6,8 +7,10 @@
; Test that AND is not removed when some lower 6 bits are not set.
define i32 @f1(i32 %a, i32 %sh) {
; CHECK-LABEL: f1:
-; CHECK: nil{{[lf]}} %r3, 31
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r3, 31
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 31
%shift = shl i32 %a, %and
ret i32 %shift
@@ -16,8 +19,9 @@ define i32 @f1(i32 %a, i32 %sh) {
; Test removal of AND mask with only bottom 6 bits set.
define i32 @f2(i32 %a, i32 %sh) {
; CHECK-LABEL: f2:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 63
%shift = shl i32 %a, %and
ret i32 %shift
@@ -26,8 +30,9 @@ define i32 @f2(i32 %a, i32 %sh) {
; Test removal of AND mask including but not limited to bottom 6 bits.
define i32 @f3(i32 %a, i32 %sh) {
; CHECK-LABEL: f3:
-; CHECK-NOT: nil{{[lf]}} %r3, 255
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 255
%shift = shl i32 %a, %and
ret i32 %shift
@@ -36,8 +41,9 @@ define i32 @f3(i32 %a, i32 %sh) {
; Test removal of AND mask from SRA.
define i32 @f4(i32 %a, i32 %sh) {
; CHECK-LABEL: f4:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sra %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 63
%shift = ashr i32 %a, %and
ret i32 %shift
@@ -46,8 +52,9 @@ define i32 @f4(i32 %a, i32 %sh) {
; Test removal of AND mask from SRL.
define i32 @f5(i32 %a, i32 %sh) {
; CHECK-LABEL: f5:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srl %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 63
%shift = lshr i32 %a, %and
ret i32 %shift
@@ -56,8 +63,9 @@ define i32 @f5(i32 %a, i32 %sh) {
; Test removal of AND mask from SLLG.
define i64 @f6(i64 %a, i64 %sh) {
; CHECK-LABEL: f6:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 63
%shift = shl i64 %a, %and
ret i64 %shift
@@ -66,8 +74,9 @@ define i64 @f6(i64 %a, i64 %sh) {
; Test removal of AND mask from SRAG.
define i64 @f7(i64 %a, i64 %sh) {
; CHECK-LABEL: f7:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srag %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 63
%shift = ashr i64 %a, %and
ret i64 %shift
@@ -76,8 +85,9 @@ define i64 @f7(i64 %a, i64 %sh) {
; Test removal of AND mask from SRLG.
define i64 @f8(i64 %a, i64 %sh) {
; CHECK-LABEL: f8:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srlg %r2, %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i64 %sh, 63
%shift = lshr i64 %a, %and
ret i64 %shift
@@ -86,8 +96,10 @@ define i64 @f8(i64 %a, i64 %sh) {
; Test that AND with two register operands is not affected.
define i32 @f9(i32 %a, i32 %b, i32 %sh) {
; CHECK-LABEL: f9:
-; CHECK: nr %r3, %r4
-; CHECK: sll %r2, 0(%r3)
+; CHECK: # %bb.0:
+; CHECK-NEXT: nr %r3, %r4
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, %b
%shift = shl i32 %a, %and
ret i32 %shift
@@ -96,9 +108,11 @@ define i32 @f9(i32 %a, i32 %b, i32 %sh) {
; Test that AND is not entirely removed if the result is reused.
define i32 @f10(i32 %a, i32 %sh) {
; CHECK-LABEL: f10:
-; CHECK: sll %r2, 0(%r3)
-; CHECK: nil{{[lf]}} %r3, 63
-; CHECK: ar %r2, %r3
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 0(%r3)
+; CHECK-NEXT: nilf %r3, 63
+; CHECK-NEXT: ar %r2, %r3
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 63
%shift = shl i32 %a, %and
%reuse = add i32 %and, %shift
@@ -108,8 +122,29 @@ define i32 @f10(i32 %a, i32 %sh) {
; Test that AND is not removed for i128 (which calls __ashlti3)
define i128 @f11(i128 %a, i32 %sh) {
; CHECK-LABEL: f11:
-; CHECK: risbg %r4, %r4, 57, 191, 0
-; CHECK: brasl %r14, __ashlti3 at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lg %r0, 8(%r3)
+; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: lg %r1, 0(%r3)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: risbg %r4, %r4, 57, 191, 0
+; CHECK-NEXT: la %r2, 176(%r15)
+; CHECK-NEXT: la %r3, 160(%r15)
+; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: brasl %r14, __ashlti3 at PLT
+; CHECK-NEXT: lg %r0, 184(%r15)
+; CHECK-NEXT: lg %r1, 176(%r15)
+; CHECK-NEXT: stg %r0, 8(%r13)
+; CHECK-NEXT: stg %r1, 0(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
+; CHECK-NEXT: br %r14
%and = and i32 %sh, 127
%ext = zext i32 %and to i128
%shift = shl i128 %a, %ext
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