[PATCH] D76153: [SimplifyCFG] try branch-to-branch simplification sooner
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 13 13:29:21 PDT 2020
spatel created this revision.
spatel added reviewers: lebedev.ri, efriedma, nlopes, aqjune.
Herald added subscribers: hiraditya, mcrosier.
The order that we try various folds within SimplifyCFG can affect the result as shown by this patch that only moves a block of code.
But I'm not sure if the existing code or the diff in the motivating case from PR32078 is valid. Is it safe to convert this chain of branches into bitwise logic? What if the branch conditions are poison?
If this is ok, then we should be able to turn the entire sequence into logic ops rather than select at the end. I haven't looked to see why that still happens. If this is not ok, then we already have a bug in SimplifyCFG.
https://reviews.llvm.org/D76153
Files:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
llvm/test/Transforms/SimplifyCFG/PR17073.ll
llvm/test/Transforms/SimplifyCFG/extract-cost.ll
Index: llvm/test/Transforms/SimplifyCFG/extract-cost.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/extract-cost.ll
+++ llvm/test/Transforms/SimplifyCFG/extract-cost.ll
@@ -37,12 +37,10 @@
; CHECK-NEXT: [[CMP0_NOT:%.*]] = xor i1 [[CMP0]], true
; CHECK-NEXT: [[CMP1_NOT:%.*]] = xor i1 [[CMP1]], true
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMP0_NOT]], [[CMP1_NOT]]
-; CHECK-NEXT: br i1 [[BRMERGE]], label [[EXIT:%.*]], label [[CMP1_TRUE:%.*]]
-; CHECK: cmp1_true:
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP2]], i1 [[CMP3]], i1 false
+; CHECK-NEXT: [[CMP2_NOT:%.*]] = xor i1 [[CMP2]], true
+; CHECK-NEXT: [[BRMERGE1:%.*]] = or i1 [[BRMERGE]], [[CMP2_NOT]]
+; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[BRMERGE1]], i1 false, i1 [[CMP3]]
; CHECK-NEXT: ret i1 [[SPEC_SELECT]]
-; CHECK: exit:
-; CHECK-NEXT: ret i1 false
;
entry:
%cmp = icmp eq <4 x i32> %a, %b
Index: llvm/test/Transforms/SimplifyCFG/PR17073.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/PR17073.ll
+++ llvm/test/Transforms/SimplifyCFG/PR17073.ll
@@ -76,12 +76,10 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TOBOOL]], label [[EXIT:%.*]], label [[BLOCK1:%.*]]
-; CHECK: block1:
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), i32* select (i1 icmp eq (i64 add (i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64), i64 2), i64 0), i32* null, i32* @a), i32* null
-; CHECK-NEXT: ret i32* [[SPEC_SELECT]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32* null
+; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[TOBOOL]], icmp eq (i32* bitcast (i8* @b to i32*), i32* @a)
+; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[TOBOOL]], i32* null, i32* select (i1 icmp eq (i64 add (i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64), i64 2), i64 0), i32* null, i32* @a)
+; CHECK-NEXT: [[STOREMERGE:%.*]] = select i1 [[BRMERGE]], i32* [[DOTMUX]], i32* null
+; CHECK-NEXT: ret i32* [[STOREMERGE]]
;
entry:
%0 = load i32, i32* @a, align 4
Index: llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
+++ llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
@@ -53,8 +53,9 @@
define i32 @tarp(i1 %c) {
; CHECK-LABEL: @tarp(
; CHECK-NEXT: bb9:
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00), i32 42, i32 927
-; CHECK-NEXT: [[MERGE:%.*]] = select i1 [[C:%.*]], i32 [[SPEC_SELECT]], i32 42
+; CHECK-NEXT: [[C_NOT:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[C_NOT]], fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00)
+; CHECK-NEXT: [[MERGE:%.*]] = select i1 [[BRMERGE]], i32 42, i32 927
; CHECK-NEXT: ret i32 [[MERGE]]
;
br i1 %c, label %bb8, label %bb9
Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
===================================================================
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -5973,6 +5973,13 @@
if (FoldBranchToCommonDest(BI, nullptr, Options.BonusInstThreshold))
return requestResimplify();
+ // Scan predecessor blocks for conditional branches.
+ for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
+ if (BranchInst *PBI = dyn_cast<BranchInst>((*PI)->getTerminator()))
+ if (PBI != BI && PBI->isConditional())
+ if (SimplifyCondBranchToCondBranch(PBI, BI, DL, TTI))
+ return requestResimplify();
+
// We have a conditional branch to two blocks that are only reachable
// from BI. We know that the condbr dominates the two blocks, so see if
// there is any identical code in the "then" and "else" blocks. If so, we
@@ -6007,13 +6014,6 @@
if (FoldCondBranchOnPHI(BI, DL, Options.AC))
return requestResimplify();
- // Scan predecessor blocks for conditional branches.
- for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
- if (BranchInst *PBI = dyn_cast<BranchInst>((*PI)->getTerminator()))
- if (PBI != BI && PBI->isConditional())
- if (SimplifyCondBranchToCondBranch(PBI, BI, DL, TTI))
- return requestResimplify();
-
// Look for diamond patterns.
if (MergeCondStores)
if (BasicBlock *PrevBB = allPredecessorsComeFromSameSource(BB))
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