[PATCH] D74338: [TableGen] Support combining AssemblerPredicates with ORs
Simon Cook via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 13 10:45:19 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa26bd4ec1652: [TableGen] Support combining AssemblerPredicates with ORs (authored by simoncook).
Changed prior to commit:
https://reviews.llvm.org/D74338?vs=246174&id=250259#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74338/new/
https://reviews.llvm.org/D74338
Files:
llvm/include/llvm/MC/MCInstPrinter.h
llvm/include/llvm/Target/Target.td
llvm/lib/MC/MCInstPrinter.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/lib/Target/Hexagon/Hexagon.td
llvm/lib/Target/Hexagon/HexagonDepArch.td
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/MipsDSPInstrFormats.td
llvm/lib/Target/Mips/MipsInstrFPU.td
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/lib/Target/SystemZ/SystemZFeatures.td
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/test/TableGen/AsmPredicateCombining.td
llvm/test/TableGen/AsmPredicateCombiningRISCV.td
llvm/test/TableGen/AsmPredicateCondsEmission.td
llvm/utils/TableGen/AsmWriterEmitter.cpp
llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
llvm/utils/TableGen/SubtargetFeatureInfo.cpp
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