[PATCH] D76134: [Hexagon] Check isInstr() before getInstr() with SUnit.
Xinglong Liao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 13 08:01:15 PDT 2020
Xinglong created this revision.
Xinglong added reviewers: kparzysz, jverma.
Xinglong added a project: LLVM.
Herald added a subscriber: hiraditya.
SUnit represent a MachineInstr in post-regalloc scheduling but SDNode in pre-regalloc scheduling. when pass -enable-hexagon-sdnode-sched to Hexagon backend with -O1 and above, this may cause an assertion failed.
Fixes PR45194.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D76134
Files:
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
Index: llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -319,11 +319,11 @@
/// dependency.
void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
SDep &Dep) const {
- MachineInstr *SrcInst = Src->getInstr();
- MachineInstr *DstInst = Dst->getInstr();
if (!Src->isInstr() || !Dst->isInstr())
return;
+ MachineInstr *SrcInst = Src->getInstr();
+ MachineInstr *DstInst = Dst->getInstr();
const HexagonInstrInfo *QII = getInstrInfo();
// Instructions with .new operands have zero latency.
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