[PATCH] D71831: [PowerPC] Exploit the rldicl + rldicl when and with mask
qshanz via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 13 01:33:12 PDT 2020
steven.zhang marked 3 inline comments as done.
steven.zhang added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4474
+ }
+
+ // We can do special handling for pattern like this.
----------------
shchenz wrote:
> I personally think the logic for the special case is a little hard to follow.
> I guess you want to convert the following imm: 0x00ffffffffff00ff,
>
> can we first treat it as imm' 0xffffffffffff00ff? and we can call normal case like above, then we get
> ```
> Val = SDValue(CurDAG->getMachineNode(PPC::RLDICL, Loc, MVT::i64, Val,
> getI64Imm(ME + 1, Loc),
> getI64Imm((MB + 63 - ME) & 63, Loc)),
>
> SDValue Ops[] = {Val, getI64Imm(63 - ME, Loc), getI64Imm(0, Loc)};
> CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
> ```
> Notice that the second `rldicl` for above normal case has no clear operation, so its mb is 0, can we add the clear for the highest 8 bits here?
> Make a call for above normal case and then clear the highest bits in the second `rldicl`?
No. The pattern is: 0x00fff00ff000. The idea is to calculate the position of [MB1, ME1] for fff, and [MB2, ME2] for ff. Then, use two rotate clear instructions to do the calculation,
================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4481
+ MB = countLeadingZeros(Imm64);
+ ME = 63 - countTrailingZeros(Imm64);
+ if (ME != 63)
----------------
shchenz wrote:
> check last bit is 1? Is it too complicated to call countTrailingZeros?
The last bit doesn't necessary to be 1. We need to get the number of trailing 0's.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4485
+
+ // Get the invert mask of [MB, ME].
+ uint64_t InvertMask =
----------------
shchenz wrote:
> ME is always 63? Why not use 63 directly?
There won't be performance difference between the two. Use ME to make the logic clear.
Repository:
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https://reviews.llvm.org/D71831/new/
https://reviews.llvm.org/D71831
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