[PATCH] D75910: [AMDGPU] Improve scheduling model for VOP3b instructions

[Jay Foad via Phabricator via llvm-commits]

foad marked 2 inline comments as done.
foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SISchedule.td:32
+// write operand of an instruction that also writes a VGPR result.
+def WriteVCC    : SchedWrite;
+
----------------
foad wrote:
> rampitec wrote:
> > The name suggests it is any VCC write, which is not so. In addition it is not always a VCC. Maybe change to WriteAuxSGPR?
> > The name suggests it is any VCC write, which is not so.
> 
> Good point. I will try to come up with a better name.
> 
> > In addition it is not always a VCC.
> 
> True but the name gives you a hint that it is //usually// VCC (i.e. we try to persuade the register allocator to use VCC, and if it does then we can use a smaller instruction encoding).
How about Write32BitAux ? The fact that it is writing an SGPR is not really important, all that matters is the latency, which should be the same as for the first def operand.

So v_addc would be [Write32Bit, Write32BitAux], v_div_scale_f64 would be [WriteDouble, WriteDoubleAux] and so on.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75910/new/

https://reviews.llvm.org/D75910