[PATCH] D76070: [AMDGPU] Add ISD::FSHR -> ALIGNBIT support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: arsenm, foad, rampitec, dstuttard.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions, I think I've gotten the operand order correct but a target expert needs to double check.

This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76070

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
  llvm/lib/Target/AMDGPU/EvergreenInstructions.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
  llvm/test/CodeGen/AMDGPU/fshl.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/permute.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll

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