[llvm] 3e53bf5 - [PowerPC32] Fix the `setcc` inconsistent result type problem

[David Tenty via llvm-commits]

Author: Xiangling Liao
Date: 2020-03-12T10:50:37-04:00
New Revision: 3e53bf5781e01784dedb7885867f39d09201ec88

URL: https://github.com/llvm/llvm-project/commit/3e53bf5781e01784dedb7885867f39d09201ec88
DIFF: https://github.com/llvm/llvm-project/commit/3e53bf5781e01784dedb7885867f39d09201ec88.diff

LOG: [PowerPC32] Fix the `setcc` inconsistent result type problem

Summary:
On 32-bit PPC target[AIX and BE], when we convert an `i64` to `f32`, a `setcc` operand expansion is needed. The expansion will set the result type of expanded `setcc` operation based on if the subtarget use CRBits or not. If the subtarget does use the CRBits, like AIX and BE, then it will set the result type to `i1`, leading to an inconsistency with original `setcc` result type[i32].
And the reason why it crashed underneath is because we don't set result type of setcc consistent in those two places.

This patch fixes this problem by setting original setcc opnode result type also with `getSetCCResultType`  interface.

Reviewers: sfertile, cebowleratibm, hubert.reinterpretcast, Xiangling_L

Reviewed By: sfertile

Subscribers: wuzish, nemanjai, hiraditya, kbarton, jsji, shchenz, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75702

Added: 
    llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 81fa59ec5a6a..e73261236cf4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8151,8 +8151,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
                                  SINT, DAG.getConstant(53, dl, MVT::i32));
       Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
                          Cond, DAG.getConstant(1, dl, MVT::i64));
-      Cond = DAG.getSetCC(dl, MVT::i32,
-                          Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
+      Cond = DAG.getSetCC(
+          dl,
+          getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
+          Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
 
       SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
     }

diff  --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
new file mode 100644
index 000000000000..e2fead90522d
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -0,0 +1,24 @@
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
+
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+
+; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
+; generated. And this testcase verifies that the operand expansion of `setcc`
+; will not crash.
+
+%struct.A = type { float }
+
+ at ll = external local_unnamed_addr global i64
+ at a = external local_unnamed_addr global %struct.A
+
+define void @foo() local_unnamed_addr {
+entry:
+  %0 = load i64, i64* @ll
+  %conv = sitofp i64 %0 to float
+  store float %conv, float* getelementptr inbounds (%struct.A, %struct.A* @a, i32 0, i32 0)
+  ret void
+}
+
+; CHECK-NOT: Unexpected setcc expansion!