[PATCH] D76043: [WebAssembly] Fix SIMD shift unrolling to avoid assertion failure

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added reviewers: aheejin, dschuff.
Herald added subscribers: llvm-commits, zzheng, sunfish, hiraditya, jgravelle-google, sbc100.
Herald added a project: LLVM.

Using the default DAG.UnrollVectorOp on v16i8 and v8i16 vectors
results in i8 or i16 nodes being inserted into the SelectionDAG. Since
those are illegal types, this causes a legalization assertion failure
for some code patterns, as uncovered by PR45178. This change unrolls
shifts manually to avoid this issue by adding and using a new optional
EVT argument to DAG.ExtractVectorElements to control the type of the
extract_element nodes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76043

Files:
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-shift-unroll.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D76043.249828.patch
Type: text/x-patch
Size: 10666 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200312/4462a810/attachment.bin>