[PATCH] D75601: [AArch64][SVE] Add intrinsics for non-temporal scatters/gathers
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 11 11:19:23 PDT 2020
sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.
LGTM
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3085
+// Every other type is fine in tablegen.
+bool AArch64DAGToDAGISel::SelectSVEShiftImm64(SDValue N, uint64_t Low,
+ uint64_t High, SDValue &Imm) {
----------------
andwar wrote:
> sdesmalen wrote:
> > Can you also create some negative tests for this change?
> If that's OK, I'll do it in a separate patch.
Okay, that's fine with me. I guess this requires adding more patterns for shifts in order to test it, so it makes sense to do that in a separate patch.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D75601/new/
https://reviews.llvm.org/D75601
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