[PATCH] D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: dsanders, simoncook, asb.
Herald added subscribers: llvm-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, volkan, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, johnrusso, rbar, hiraditya, rovka.
Herald added a project: LLVM.

This patch generates TableGen descriptions for the specified register banks which contain a list of register sizes corresponding to the available HwModes. The appropriate size is used during codegen according to the current HwMode. As this HwMode was not available on generation, it is set upon construction of the RegisterBankInfo class. Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor.

The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76007

Files:
  llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
  llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
  llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
  llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/utils/TableGen/RegisterBankEmitter.cpp

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