[PATCH] D76006: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: dsanders, simoncook.
Herald added subscribers: llvm-commits, rovka.
Herald added a project: LLVM.

This patch rewrites the RegisterBankEmitter class to derive RegisterClassHierarchy from CodeGenTarget::getRegBank() rather than constructing our own copy. All are now accessed through a const reference.

This appeared to fix a case of invalidating vectors within RegisterClassHierarchy.getHwModes() - found when testing implementations for another RegisterBankEmitter patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76006

Files:
  llvm/utils/TableGen/CodeGenRegisters.cpp
  llvm/utils/TableGen/CodeGenRegisters.h
  llvm/utils/TableGen/RegisterBankEmitter.cpp

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