[PATCH] D75990: [ARM] MVE VFMA (reg) and VFMAS patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: simon_tatham, SjoerdMeijer, samparker, ostannard, t.p.northover.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

These two instructions perform floating point fused multiply add using a GPR as one of the operands. As a result they select from a splat. VFMAS is `q*q+r` and  VFMA is `q*r + q`

These, like the other floating point instruction using a gpr, will not be used a lot yet as the splat will not be sunk into loops. This will require some extra work to make sure that copies from fpr to gpr do not get stuck in the loop.


https://reviews.llvm.org/D75990

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-fmas.ll


Index: llvm/test/CodeGen/Thumb2/mve-fmas.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-fmas.ll
+++ llvm/test/CodeGen/Thumb2/mve-fmas.ll
@@ -208,8 +208,7 @@
 ; CHECK-MVE-VMLA:       @ %bb.0: @ %entry
 ; CHECK-MVE-VMLA-NEXT:    vcvtb.f16.f32 s8, s8
 ; CHECK-MVE-VMLA-NEXT:    vmov r0, s8
-; CHECK-MVE-VMLA-NEXT:    vdup.16 q2, r0
-; CHECK-MVE-VMLA-NEXT:    vfma.f16 q0, q1, q2
+; CHECK-MVE-VMLA-NEXT:    vfma.f16 q0, q1, r0
 ; CHECK-MVE-VMLA-NEXT:    bx lr
 ;
 ; CHECK-MVE-LABEL: vfmar16:
@@ -275,9 +274,7 @@
 ; CHECK-MVE-VMLA:       @ %bb.0: @ %entry
 ; CHECK-MVE-VMLA-NEXT:    vcvtb.f16.f32 s8, s8
 ; CHECK-MVE-VMLA-NEXT:    vmov r0, s8
-; CHECK-MVE-VMLA-NEXT:    vdup.16 q2, r0
-; CHECK-MVE-VMLA-NEXT:    vfma.f16 q2, q0, q1
-; CHECK-MVE-VMLA-NEXT:    vmov q0, q2
+; CHECK-MVE-VMLA-NEXT:    vfmas.f16 q0, q1, r0
 ; CHECK-MVE-VMLA-NEXT:    bx lr
 ;
 ; CHECK-MVE-LABEL: vfma16:
@@ -419,8 +416,7 @@
 ; CHECK-MVE-VMLA-LABEL: vfmar32:
 ; CHECK-MVE-VMLA:       @ %bb.0: @ %entry
 ; CHECK-MVE-VMLA-NEXT:    vmov r0, s8
-; CHECK-MVE-VMLA-NEXT:    vdup.32 q2, r0
-; CHECK-MVE-VMLA-NEXT:    vfma.f32 q0, q1, q2
+; CHECK-MVE-VMLA-NEXT:    vfma.f32 q0, q1, r0
 ; CHECK-MVE-VMLA-NEXT:    bx lr
 ;
 ; CHECK-MVE-LABEL: vfmar32:
@@ -449,9 +445,7 @@
 ; CHECK-MVE-VMLA-LABEL: vfmas32:
 ; CHECK-MVE-VMLA:       @ %bb.0: @ %entry
 ; CHECK-MVE-VMLA-NEXT:    vmov r0, s8
-; CHECK-MVE-VMLA-NEXT:    vdup.32 q2, r0
-; CHECK-MVE-VMLA-NEXT:    vfma.f32 q2, q0, q1
-; CHECK-MVE-VMLA-NEXT:    vmov q0, q2
+; CHECK-MVE-VMLA-NEXT:    vfmas.f32 q0, q1, r0
 ; CHECK-MVE-VMLA-NEXT:    bx lr
 ;
 ; CHECK-MVE-LABEL: vfmas32:
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -5235,6 +5235,18 @@
   def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>;
 }
 
+let Predicates = [HasMVEFloat] in {
+  def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 (ARMvdup SPR:$v2)), (v4f32 MQPR:$src3))),
+            (v4f32 (MVE_VFMA_qr_f32 $src3, $src1, (i32 (COPY_TO_REGCLASS (f32 SPR:$v2), rGPR))))>;
+  def : Pat<(v8f16 (fma (v8f16 MQPR:$src1), (v8f16 (ARMvdup HPR:$v2)), (v8f16 MQPR:$src3))),
+            (v8f16 (MVE_VFMA_qr_f16 $src3, $src1, (i32 (COPY_TO_REGCLASS (f16 HPR:$v2), rGPR))))>;
+
+  def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 MQPR:$src2), (v4f32 (ARMvdup SPR:$v3)))),
+            (v4f32 (MVE_VFMA_qr_Sf32 $src1, $src2, (i32 (COPY_TO_REGCLASS (f32 SPR:$v3), rGPR))))>;
+  def : Pat<(v8f16 (fma (v8f16 MQPR:$src1), (v8f16 MQPR:$src2), (v8f16 (ARMvdup HPR:$v3)))),
+            (v8f16 (MVE_VFMA_qr_Sf16 $src1, $src2, (i32 (COPY_TO_REGCLASS (f16 HPR:$v3), rGPR))))>;
+}
+
 class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
                      bit bit_5, bit bit_12, list<dag> pattern=[]>
   : MVE_qDestSrc_rSrc<iname, suffix, pattern> {


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