[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 10 13:39:55 PDT 2020
efriedma accepted this revision.
efriedma added a comment.
LGTM with one minor comment.
================
Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:3622
+ SelectAddrMode3(Addr, Base, RegOffset, ImmOffset);
+ if (RegOffset != CurDAG->getRegister(0, MVT::i32)) {
+ Base = Addr;
----------------
The RegOffset check could use a comment explaining what it's doing, here and for STRD.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70072/new/
https://reviews.llvm.org/D70072
More information about the llvm-commits
mailing list