[PATCH] D75941: [x86][seses] No LFENCEs in basic blocks w/o loads
Zola Bridges via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 10 10:19:35 PDT 2020
zbrid created this revision.
Herald added subscribers: llvm-commits, jfb, hiraditya.
Herald added a project: LLVM.
zbrid added a reviewer: craig.topper.
Add a flag to the x86 Speculative Execution Side Effect Suppression Pass
that allows users to turn off adding LFENCEs in basic blocks with no
loads.
This is a part of a set of flags that can be used to experiment with
optimizing this mitigation for Load Value Injection.
One pager on Load Value Injection:
https://software.intel.com/security-software-guidance/software-guidance/load-value-injection
Deep dive on Load Value Injection:
https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
Results of my performance testing
I ran the BoringSSL benchmarks which run many cryptographic operations
and reports the number of operations per second completed in a given
time.
Modified Mitigation vs Baseline
Geometric mean
0.073 (This can be read as the geomean ops/s of the mitigated program
was 7.3% of the ops/s of the unmitigated program. Similar below.)
Minimum
0.041
Quartile 1
0.060
Median
0.066
Quartile 3
0.081
Maximum
0.234
Fully Mitigated vs Baseline
Geometric mean
0.071
Minimum
0.041
Quartile 1
0.060
Median
0.063
Quartile 3
0.077
Maximum
0.230
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D75941
Files:
llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll
Index: llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable -x86-seses-omit-lfence-in-bb-without-loads %s -o - | FileCheck %s --check-prefix=CHECK-FLAGGED
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable %s -o - | FileCheck %s --check-prefix=CHECK-FULL
+
+define dso_local void @_Z4buzzv() {
+entry:
+ %a = alloca i32, align 4
+ store i32 10, i32* %a, align 4
+ ret void
+}
+
+; CHECK-FLAGGED: .globl _Z4buzzv # -- Begin function _Z4buzzv
+; CHECK-FLAGGED: .p2align 4, 0x90
+; CHECK-FLAGGED: .type _Z4buzzv, at function
+; CHECK-FLAGGED:_Z4buzzv: # @_Z4buzzv
+; CHECK-FLAGGED:.L_Z4buzzv$local:
+; CHECK-FLAGGED: .cfi_startproc
+; CHECK-FLAGGED:# %bb.0: # %entry
+; CHECK-FLAGGED: movl $10, -4(%rsp)
+; CHECK-FLAGGED: retq
+; CHECK-FLAGGED:.Lfunc_end0:
+; CHECK-FLAGGED: .size _Z4buzzv, .Lfunc_end0-_Z4buzzv
+; CHECK-FLAGGED: .cfi_endproc
+; CHECK-FLAGGED: # -- End function
+; CHECK-FLAGGED: .section ".note.GNU-stack","", at progbits
+
+
+; CHECK-FULL: .globl _Z4buzzv # -- Begin function _Z4buzzv
+; CHECK-FULL: .p2align 4, 0x90
+; CHECK-FULL: .type _Z4buzzv, at function
+; CHECK-FULL:_Z4buzzv: # @_Z4buzzv
+; CHECK-FULL:.L_Z4buzzv$local:
+; CHECK-FULL: .cfi_startproc
+; CHECK-FULL:# %bb.0: # %entry
+; CHECK-FULL: lfence
+; CHECK-FULL: movl $10, -4(%rsp)
+; CHECK-FULL: retq
+; CHECK-FULL:.Lfunc_end0:
+; CHECK-FULL: .size _Z4buzzv, .Lfunc_end0-_Z4buzzv
+; CHECK-FULL: .cfi_endproc
+; CHECK-FULL: # -- End function
+; CHECK-FULL: .section ".note.GNU-stack","", at progbits
Index: llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
===================================================================
--- llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
+++ llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
@@ -50,6 +50,11 @@
cl::desc("Omit all lfences before branch instructions."),
cl::init(false), cl::Hidden);
+static cl::opt<bool>
+ OmitLFENCEInBasicBlocksWithoutLoads("x86-seses-omit-lfence-in-bb-without-loads",
+ cl::desc("Omit LFENCE in basic blocks without any loads even if there are stores."),
+ cl::init(false), cl::Hidden);
+
static bool hasConstantAddressingMode(const MachineInstr &MI);
namespace {
@@ -81,6 +86,20 @@
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
const X86InstrInfo *TII = Subtarget.getInstrInfo();
for (MachineBasicBlock &MBB : MF) {
+ if (OmitLFENCEInBasicBlocksWithoutLoads) {
+
+ bool FoundLoad = false;
+ for (const MachineInstr &MI : MBB) {
+ if (MI.mayLoad()) {
+ FoundLoad = true;
+ break;
+ }
+ }
+ if (!FoundLoad) {
+ continue;
+ }
+ }
+
MachineInstr *FirstTerminator = nullptr;
for (auto &MI : MBB) {
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