[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

Victor Campos via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 10 10:19:35 PDT 2020


vhscampos updated this revision to Diff 249434.
vhscampos added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: danielkiss.

Changes:

1. Explictly avoid using the register-offset variant of LDRD/STRD. This variant has a limitation on register allocation: the register allocated to the register-offset cannot be reused in any of the remaining operands. I could not find an easy way to implement this in LLVM, so I left it as a to-do in the future.
2. Instruction selection of STRD was moved from TableGen to C++ because of point (1).
3. Updated tests to reflect these changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

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