[PATCH] D75601: [AArch64][SVE] Add intrinsics for non-temporal scatters/gathers
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 10 08:40:03 PDT 2020
sdesmalen added a comment.
Maybe you can avoid the need for `SSTNT1_INDEX` and `GLDNT1_INDEX` by refactoring the performScatterStoreCombine/performGatherLoadCombine to take the parameters from the caller, rather than handling the special cases inside that function.
I don't think that should hold off this patch though, but maybe something to refactor afterwards.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3085
+// Every other type is fine in tablegen.
+bool AArch64DAGToDAGISel::SelectSVEShiftImm64(SDValue N, uint64_t Low,
+ uint64_t High, SDValue &Imm) {
----------------
Can you also create some negative tests for this change?
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12674
+ if (Opcode == AArch64ISD::SSTNT1_INDEX) {
+ Offset = getScaledOffsetForLDNT1(DAG, Offset, DL, SrcElVT.getSizeInBits());
+ Opcode = AArch64ISD::SSTNT1;
----------------
getScaledOffsetForLDNT1 is a bit of misnomer in this function, how about `getScaledOffsetForBitwidth()`?
Repository:
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https://reviews.llvm.org/D75601/new/
https://reviews.llvm.org/D75601
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