[llvm] e71fb46 - [TargetLowering] SimplifyDemandedVectorElts - add DemandedElts mask to ISD::BITCAST SimplifyDemandedBits call.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 10 06:39:32 PDT 2020
Author: Simon Pilgrim
Date: 2020-03-10T13:39:10Z
New Revision: e71fb46a8fd15fedb763c7bf6a234bdd15022180
URL: https://github.com/llvm/llvm-project/commit/e71fb46a8fd15fedb763c7bf6a234bdd15022180
DIFF: https://github.com/llvm/llvm-project/commit/e71fb46a8fd15fedb763c7bf6a234bdd15022180.diff
LOG: [TargetLowering] SimplifyDemandedVectorElts - add DemandedElts mask to ISD::BITCAST SimplifyDemandedBits call.
This fixes most of the regressions introduced in the rG4bc6f6332028 bugfix. The vector-trunc.ll issue should be fixed by D66004.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
llvm/test/CodeGen/X86/load-partial.ll
llvm/test/CodeGen/X86/packss.ll
llvm/test/CodeGen/X86/pr30562.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/vector-mul.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-v1.ll
llvm/test/CodeGen/X86/vector-trunc-math.ll
llvm/test/CodeGen/X86/vector-trunc.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 27a7cbe8a191..7b27eccbfc6c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2310,7 +2310,8 @@ bool TargetLowering::SimplifyDemandedVectorElts(
}
KnownBits Known;
- if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1))
+ if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcDemandedElts, Known,
+ TLO, Depth + 1))
return true;
}
diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
index a77ad21105df..fca185fb3d49 100644
--- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
+++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
@@ -367,10 +367,10 @@ define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signe
; CHECK-NEXT: vsplth v2, v2, 3
; CHECK-NEXT: addis r3, r2, .LCPI3_0 at toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI3_0 at toc@l
-; CHECK-NEXT: vmrglh v4, v3, v4
; CHECK-NEXT: vmrglh v2, v3, v2
-; CHECK-NEXT: vsplth v3, v3, 7
-; CHECK-NEXT: vmrglw v3, v4, v3
+; CHECK-NEXT: vmrglh v3, v3, v4
+; CHECK-NEXT: xxlxor v4, v4, v4
+; CHECK-NEXT: vmrglw v3, v3, v4
; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v2, v3, v4
diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
index e40c348fcb87..d795f6b62fab 100644
--- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
@@ -1071,6 +1071,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: mulld r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32
+; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 9
@@ -1079,9 +1080,6 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
-; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@@ -1096,7 +1094,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: xxswapd v4, vs0
+; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
@@ -1181,6 +1179,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8LE-NEXT: lis r3, 24749
; P8LE-NEXT: lis r8, -19946
; P8LE-NEXT: lis r10, -14230
+; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 47143
; P8LE-NEXT: ori r8, r8, 17097
; P8LE-NEXT: mfvsrd r4, f0
@@ -1213,21 +1212,18 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8LE-NEXT: mulli r3, r3, 5423
; P8LE-NEXT: add r7, r7, r9
; P8LE-NEXT: mulli r8, r8, 23
-; P8LE-NEXT: li r9, 0
; P8LE-NEXT: mulli r7, r7, 654
-; P8LE-NEXT: mtvsrd f0, r9
; P8LE-NEXT: subf r3, r3, r5
-; P8LE-NEXT: xxswapd v4, vs0
-; P8LE-NEXT: subf r5, r8, r6
+; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: subf r3, r8, r6
+; P8LE-NEXT: subf r4, r7, r4
; P8LE-NEXT: mtvsrd f1, r3
-; P8LE-NEXT: subf r3, r7, r4
-; P8LE-NEXT: mtvsrd f2, r5
-; P8LE-NEXT: mtvsrd f3, r3
-; P8LE-NEXT: xxswapd v2, vs1
-; P8LE-NEXT: xxswapd v3, vs2
-; P8LE-NEXT: xxswapd v5, vs3
+; P8LE-NEXT: mtvsrd f2, r4
+; P8LE-NEXT: xxswapd v2, vs0
+; P8LE-NEXT: xxswapd v3, vs1
+; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3
-; P8LE-NEXT: vmrglh v3, v5, v4
+; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
;
@@ -1332,11 +1328,9 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
-; P9LE-NEXT: li r3, 0
; P9LE-NEXT: xxswapd v2, vs0
-; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: vmrglh v3, v4, v3
-; P9LE-NEXT: xxswapd v4, vs0
+; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr
@@ -1394,49 +1388,47 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P8LE-LABEL: dont_fold_urem_i16_smax:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, 24749
-; P8LE-NEXT: lis r8, -19946
-; P8LE-NEXT: ori r3, r3, 47143
-; P8LE-NEXT: ori r8, r8, 17097
-; P8LE-NEXT: mfvsrd r4, f0
-; P8LE-NEXT: rldicl r5, r4, 16, 48
-; P8LE-NEXT: rldicl r6, r4, 32, 48
-; P8LE-NEXT: extsh r7, r5
-; P8LE-NEXT: extsh r9, r6
-; P8LE-NEXT: extsw r7, r7
+; P8LE-NEXT: lis r6, 24749
+; P8LE-NEXT: lis r7, -19946
+; P8LE-NEXT: xxlxor v5, v5, v5
+; P8LE-NEXT: ori r6, r6, 47143
+; P8LE-NEXT: ori r7, r7, 17097
+; P8LE-NEXT: mfvsrd r3, f0
+; P8LE-NEXT: rldicl r4, r3, 16, 48
+; P8LE-NEXT: rldicl r5, r3, 32, 48
+; P8LE-NEXT: extsh r8, r4
+; P8LE-NEXT: extsh r9, r5
+; P8LE-NEXT: extsw r8, r8
; P8LE-NEXT: extsw r9, r9
-; P8LE-NEXT: mulld r3, r7, r3
-; P8LE-NEXT: mulld r7, r9, r8
-; P8LE-NEXT: rldicl r4, r4, 48, 48
-; P8LE-NEXT: rldicl r8, r3, 1, 63
-; P8LE-NEXT: rldicl r3, r3, 32, 32
+; P8LE-NEXT: mulld r6, r8, r6
+; P8LE-NEXT: mulld r7, r9, r7
+; P8LE-NEXT: rldicl r3, r3, 48, 48
+; P8LE-NEXT: rldicl r8, r6, 32, 32
; P8LE-NEXT: rldicl r7, r7, 32, 32
-; P8LE-NEXT: srawi r3, r3, 11
+; P8LE-NEXT: rldicl r6, r6, 1, 63
+; P8LE-NEXT: srawi r8, r8, 11
; P8LE-NEXT: add r7, r7, r9
-; P8LE-NEXT: add r3, r3, r8
-; P8LE-NEXT: li r9, 0
+; P8LE-NEXT: add r6, r8, r6
; P8LE-NEXT: srwi r8, r7, 31
; P8LE-NEXT: srawi r7, r7, 4
-; P8LE-NEXT: mtvsrd f0, r9
-; P8LE-NEXT: mulli r3, r3, 5423
+; P8LE-NEXT: mulli r6, r6, 5423
; P8LE-NEXT: add r7, r7, r8
-; P8LE-NEXT: extsh r8, r4
+; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: mulli r7, r7, 23
; P8LE-NEXT: srawi r8, r8, 15
-; P8LE-NEXT: xxswapd v4, vs0
-; P8LE-NEXT: subf r3, r3, r5
-; P8LE-NEXT: addze r5, r8
-; P8LE-NEXT: slwi r5, r5, 15
-; P8LE-NEXT: subf r6, r7, r6
-; P8LE-NEXT: mtvsrd f1, r3
-; P8LE-NEXT: subf r3, r5, r4
-; P8LE-NEXT: mtvsrd f2, r6
-; P8LE-NEXT: mtvsrd f3, r3
-; P8LE-NEXT: xxswapd v2, vs1
-; P8LE-NEXT: xxswapd v3, vs2
-; P8LE-NEXT: xxswapd v5, vs3
+; P8LE-NEXT: subf r4, r6, r4
+; P8LE-NEXT: addze r6, r8
+; P8LE-NEXT: mtvsrd f0, r4
+; P8LE-NEXT: slwi r4, r6, 15
+; P8LE-NEXT: subf r5, r7, r5
+; P8LE-NEXT: subf r3, r4, r3
+; P8LE-NEXT: mtvsrd f1, r5
+; P8LE-NEXT: xxswapd v2, vs0
+; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: xxswapd v3, vs1
+; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3
-; P8LE-NEXT: vmrglh v3, v5, v4
+; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
;
diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
index e1d051d6f3cf..e3d9027d9e98 100644
--- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
@@ -1006,11 +1006,9 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
-; P9LE-NEXT: li r3, 0
; P9LE-NEXT: xxswapd v2, vs0
-; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: vmrglh v3, v4, v3
-; P9LE-NEXT: xxswapd v4, vs0
+; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr
@@ -1066,43 +1064,41 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: li r3, 0
-; P8LE-NEXT: lis r9, 24749
-; P8LE-NEXT: oris r5, r3, 51306
-; P8LE-NEXT: oris r3, r3, 45590
-; P8LE-NEXT: ori r9, r9, 47143
-; P8LE-NEXT: ori r5, r5, 30865
-; P8LE-NEXT: ori r3, r3, 17097
+; P8LE-NEXT: lis r8, 24749
+; P8LE-NEXT: xxlxor v5, v5, v5
+; P8LE-NEXT: oris r5, r3, 45590
+; P8LE-NEXT: ori r8, r8, 47143
+; P8LE-NEXT: oris r3, r3, 51306
+; P8LE-NEXT: ori r5, r5, 17097
+; P8LE-NEXT: ori r3, r3, 30865
; P8LE-NEXT: mfvsrd r4, f0
-; P8LE-NEXT: rldicl r6, r4, 48, 48
-; P8LE-NEXT: rldicl r7, r4, 32, 48
-; P8LE-NEXT: rlwinm r8, r6, 31, 17, 31
-; P8LE-NEXT: rldicl r4, r4, 16, 48
-; P8LE-NEXT: mulld r5, r8, r5
-; P8LE-NEXT: rlwinm r8, r7, 0, 16, 31
-; P8LE-NEXT: mulld r3, r8, r3
-; P8LE-NEXT: rlwinm r8, r4, 0, 16, 31
-; P8LE-NEXT: mulld r8, r8, r9
-; P8LE-NEXT: li r9, 0
-; P8LE-NEXT: mtvsrd f0, r9
-; P8LE-NEXT: rldicl r5, r5, 24, 40
-; P8LE-NEXT: rldicl r3, r3, 28, 36
-; P8LE-NEXT: mulli r5, r5, 654
-; P8LE-NEXT: xxswapd v2, vs0
+; P8LE-NEXT: rldicl r6, r4, 32, 48
+; P8LE-NEXT: rldicl r7, r4, 16, 48
+; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
+; P8LE-NEXT: rldicl r4, r4, 48, 48
+; P8LE-NEXT: mulld r5, r9, r5
+; P8LE-NEXT: rlwinm r9, r7, 0, 16, 31
+; P8LE-NEXT: mulld r8, r9, r8
+; P8LE-NEXT: rlwinm r9, r4, 31, 17, 31
+; P8LE-NEXT: mulld r3, r9, r3
+; P8LE-NEXT: rldicl r5, r5, 28, 36
; P8LE-NEXT: rldicl r8, r8, 21, 43
-; P8LE-NEXT: mulli r3, r3, 23
+; P8LE-NEXT: mulli r5, r5, 23
+; P8LE-NEXT: rldicl r3, r3, 24, 40
; P8LE-NEXT: mulli r8, r8, 5423
+; P8LE-NEXT: mulli r3, r3, 654
; P8LE-NEXT: subf r5, r5, r6
-; P8LE-NEXT: subf r3, r3, r7
-; P8LE-NEXT: mtvsrd f1, r5
-; P8LE-NEXT: subf r4, r8, r4
+; P8LE-NEXT: subf r6, r8, r7
+; P8LE-NEXT: mtvsrd f0, r5
+; P8LE-NEXT: subf r3, r3, r4
+; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtvsrd f2, r3
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
-; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v2, v3, v2
-; P8LE-NEXT: vmrglh v3, v5, v4
-; P8LE-NEXT: vmrglw v2, v3, v2
+; P8LE-NEXT: vmrglh v3, v4, v5
+; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
;
; P8BE-LABEL: dont_fold_urem_one:
diff --git a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
index 900e5146cb9e..8d7aad4d6a3e 100644
--- a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
+++ b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
@@ -1400,9 +1400,7 @@ define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
; AVX-64-LABEL: f4xi64_i128:
; AVX-64: # %bb.0:
; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: movl $1, %eax
-; AVX-64-NEXT: vmovq %rax, %xmm2
-; AVX-64-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
+; AVX-64-NEXT: vmovdqa {{.*#+}} xmm2 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; AVX-64-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; AVX-64-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -1460,9 +1458,7 @@ define <8 x i64> @f8xi64_i128(<8 x i64> %a) {
; AVX-64-LABEL: f8xi64_i128:
; AVX-64: # %bb.0:
; AVX-64-NEXT: vextractf128 $1, %ymm1, %xmm2
-; AVX-64-NEXT: movl $1, %eax
-; AVX-64-NEXT: vmovq %rax, %xmm3
-; AVX-64-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
+; AVX-64-NEXT: vmovdqa {{.*#+}} xmm3 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; AVX-64-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX-64-NEXT: vpaddq %xmm3, %xmm1, %xmm1
; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1470,7 +1466,7 @@ define <8 x i64> @f8xi64_i128(<8 x i64> %a) {
; AVX-64-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX-64-NEXT: vpaddq %xmm3, %xmm0, %xmm0
; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX-64-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [0,1,0,1]
+; AVX-64-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; AVX-64-NEXT: # ymm2 = mem[0,1,0,1]
; AVX-64-NEXT: vandps %ymm2, %ymm0, %ymm0
; AVX-64-NEXT: vandps %ymm2, %ymm1, %ymm1
@@ -1539,9 +1535,7 @@ define <8 x i64> @f8xi64_i256(<8 x i64> %a) {
; AVX-64-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX-64-NEXT: vmovdqa {{.*#+}} xmm3 = [2,3]
; AVX-64-NEXT: vpaddq %xmm3, %xmm2, %xmm2
-; AVX-64-NEXT: movl $1, %eax
-; AVX-64-NEXT: vmovq %rax, %xmm4
-; AVX-64-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
+; AVX-64-NEXT: vmovdqa {{.*#+}} xmm4 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; AVX-64-NEXT: vpaddq %xmm4, %xmm1, %xmm1
; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm2
diff --git a/llvm/test/CodeGen/X86/load-partial.ll b/llvm/test/CodeGen/X86/load-partial.ll
index 4a0a52903d0b..4e1014fa28a7 100644
--- a/llvm/test/CodeGen/X86/load-partial.ll
+++ b/llvm/test/CodeGen/X86/load-partial.ll
@@ -307,25 +307,17 @@ define i32 @load_partial_illegal_type() {
; SSE2: # %bb.0:
; SSE2-NEXT: movzwl {{.*}}(%rip), %eax
; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm1, %xmm0
-; SSE2-NEXT: movl $2, %eax
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: pslld $16, %xmm2
-; SSE2-NEXT: pandn %xmm2, %xmm1
-; SSE2-NEXT: por %xmm0, %xmm1
-; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: por {{.*}}(%rip), %xmm0
+; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_partial_illegal_type:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movzwl {{.*}}(%rip), %eax
; SSSE3-NEXT: movd %eax, %xmm0
-; SSSE3-NEXT: movl $2, %eax
-; SSSE3-NEXT: movd %eax, %xmm1
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,xmm0[3,4,5,6,7,8,9,10,11,12,13,14,15]
-; SSSE3-NEXT: por %xmm1, %xmm0
+; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
; SSSE3-NEXT: movd %xmm0, %eax
; SSSE3-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
index e3bd9d9e6ed1..4eed19a4fab9 100644
--- a/llvm/test/CodeGen/X86/packss.ll
+++ b/llvm/test/CodeGen/X86/packss.ll
@@ -158,8 +158,9 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllq $63, %xmm1
; X86-SSE-NEXT: psllq $63, %xmm0
+; X86-SSE-NEXT: movl $1, %eax
+; X86-SSE-NEXT: movd %eax, %xmm2
; X86-SSE-NEXT: psrlq $63, %xmm0
-; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4.9406564584124654E-324,-0.0E+0]
; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: psubq %xmm2, %xmm0
; X86-SSE-NEXT: psrlq $63, %xmm1
@@ -173,17 +174,18 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) {
; X86-AVX1-LABEL: trunc_ashr_v4i64_demandedelts:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpsllq $63, %xmm0, %xmm1
-; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; X86-AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
-; X86-AVX1-NEXT: vpsrlq $63, %xmm2, %xmm2
-; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,0,0,2147483648]
-; X86-AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
-; X86-AVX1-NEXT: vpsubq %xmm3, %xmm2, %xmm2
+; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; X86-AVX1-NEXT: vpsllq $63, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpsrlq $63, %xmm0, %xmm0
+; X86-AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [1,1]
+; X86-AVX1-NEXT: # xmm2 = mem[0,0]
+; X86-AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; X86-AVX1-NEXT: vpaddq %xmm3, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlq $63, %xmm1, %xmm1
-; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
-; X86-AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0
-; X86-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; X86-AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
+; X86-AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
+; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4]
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
@@ -225,17 +227,16 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) {
; X64-AVX1-LABEL: trunc_ashr_v4i64_demandedelts:
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpsllq $63, %xmm0, %xmm1
-; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; X64-AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
-; X64-AVX1-NEXT: vpsrlq $63, %xmm2, %xmm2
-; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,9223372036854775808]
-; X64-AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
-; X64-AVX1-NEXT: vpsubq %xmm3, %xmm2, %xmm2
+; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; X64-AVX1-NEXT: vpsllq $63, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpsrlq $63, %xmm0, %xmm0
+; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,9223372036854775808]
+; X64-AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrlq $63, %xmm1, %xmm1
-; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
-; X64-AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0
-; X64-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; X64-AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
+; X64-AVX1-NEXT: vpsubq %xmm2, %xmm1, %xmm1
+; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4]
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/pr30562.ll b/llvm/test/CodeGen/X86/pr30562.ll
index 24cbf10ed53d..05d5c09d55b9 100644
--- a/llvm/test/CodeGen/X86/pr30562.ll
+++ b/llvm/test/CodeGen/X86/pr30562.ll
@@ -6,20 +6,18 @@ define i32 @foo(i64* nocapture %perm, i32 %n) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: movl $1, %ecx
-; CHECK-NEXT: movq %rcx, %xmm0
-; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; CHECK-NEXT: movl %esi, %ecx
; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2,3]
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [2,3]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -24(%rsp,%rcx,8), %rdx
-; CHECK-NEXT: movdqu %xmm0, (%rdi,%rdx,8)
+; CHECK-NEXT: movups %xmm0, (%rdi,%rdx,8)
; CHECK-NEXT: testq %rdx, %rdx
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
diff --git a/llvm/test/CodeGen/X86/shrink_vmul.ll b/llvm/test/CodeGen/X86/shrink_vmul.ll
index 1c1032a4c321..42416fb47f99 100644
--- a/llvm/test/CodeGen/X86/shrink_vmul.ll
+++ b/llvm/test/CodeGen/X86/shrink_vmul.ll
@@ -1948,11 +1948,9 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,65536,u,u>
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm1
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
@@ -1974,11 +1972,9 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm1, %xmm1
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,65536,u,u>
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm2, %xmm1
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; X64-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
@@ -2018,11 +2014,9 @@ define void @mul_2xi16_varconst4(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0
-; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,32768,u,u>
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm1
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl
@@ -2044,11 +2038,9 @@ define void @mul_2xi16_varconst4(i8* nocapture readonly %a, i64 %index) {
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0
-; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,32768,u,u>
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm2, %xmm1
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; X64-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-mul.ll b/llvm/test/CodeGen/X86/vector-mul.ll
index b8ace4effe88..805ff9f69ed5 100644
--- a/llvm/test/CodeGen/X86/vector-mul.ll
+++ b/llvm/test/CodeGen/X86/vector-mul.ll
@@ -1531,9 +1531,7 @@ define <2 x i64> @mul_v2i64_0_1(<2 x i64> %a0) nounwind {
;
; X64-LABEL: mul_v2i64_0_1:
; X64: # %bb.0:
-; X64-NEXT: movl $1, %eax
-; X64-NEXT: movq %rax, %xmm1
-; X64-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; X64-NEXT: movdqa %xmm0, %xmm2
; X64-NEXT: pmuludq %xmm1, %xmm2
; X64-NEXT: psrlq $32, %xmm0
@@ -1544,9 +1542,7 @@ define <2 x i64> @mul_v2i64_0_1(<2 x i64> %a0) nounwind {
;
; X64-XOP-LABEL: mul_v2i64_0_1:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: movl $1, %eax
-; X64-XOP-NEXT: vmovq %rax, %xmm1
-; X64-XOP-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
+; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm0
; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1556,9 +1552,7 @@ define <2 x i64> @mul_v2i64_0_1(<2 x i64> %a0) nounwind {
;
; X64-AVX2-LABEL: mul_v2i64_0_1:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: movl $1, %eax
-; X64-AVX2-NEXT: vmovq %rax, %xmm1
-; X64-AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
+; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0]
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -1568,10 +1562,7 @@ define <2 x i64> @mul_v2i64_0_1(<2 x i64> %a0) nounwind {
;
; X64-AVX512DQ-LABEL: mul_v2i64_0_1:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: movl $1, %eax
-; X64-AVX512DQ-NEXT: vmovq %rax, %xmm1
-; X64-AVX512DQ-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; X64-AVX512DQ-NEXT: vpmullq %xmm1, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 0, i64 1>
ret <2 x i64> %1
@@ -1595,62 +1586,45 @@ define <2 x i64> @mul_v2i64_neg_0_1(<2 x i64> %a0) nounwind {
;
; X64-LABEL: mul_v2i64_neg_0_1:
; X64: # %bb.0:
-; X64-NEXT: movdqa %xmm0, %xmm1
-; X64-NEXT: psrlq $32, %xmm1
-; X64-NEXT: movq $-1, %rax
-; X64-NEXT: movq %rax, %xmm2
-; X64-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
-; X64-NEXT: pmuludq %xmm2, %xmm1
-; X64-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-NEXT: movq %rax, %xmm3
-; X64-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-NEXT: pmuludq %xmm0, %xmm3
-; X64-NEXT: paddq %xmm1, %xmm3
-; X64-NEXT: psllq $32, %xmm3
-; X64-NEXT: pmuludq %xmm2, %xmm0
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255]
+; X64-NEXT: movdqa %xmm0, %xmm2
+; X64-NEXT: pmuludq %xmm1, %xmm2
+; X64-NEXT: movdqa %xmm0, %xmm3
+; X64-NEXT: psrlq $32, %xmm3
+; X64-NEXT: pmuludq %xmm1, %xmm3
+; X64-NEXT: pmuludq {{.*}}(%rip), %xmm0
; X64-NEXT: paddq %xmm3, %xmm0
+; X64-NEXT: psllq $32, %xmm0
+; X64-NEXT: paddq %xmm2, %xmm0
; X64-NEXT: retq
;
; X64-XOP-LABEL: mul_v2i64_neg_0_1:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm1
-; X64-XOP-NEXT: movq $-1, %rax
-; X64-XOP-NEXT: vmovq %rax, %xmm2
-; X64-XOP-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
-; X64-XOP-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
-; X64-XOP-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-XOP-NEXT: vmovq %rax, %xmm3
-; X64-XOP-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-XOP-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
-; X64-XOP-NEXT: vpaddq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpsllq $32, %xmm1, %xmm1
-; X64-XOP-NEXT: vpmuludq %xmm2, %xmm0, %xmm0
+; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255]
+; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
+; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
+; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
+; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v2i64_neg_0_1:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm1
-; X64-AVX2-NEXT: movq $-1, %rax
-; X64-AVX2-NEXT: vmovq %rax, %xmm2
-; X64-AVX2-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
-; X64-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
-; X64-AVX2-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-AVX2-NEXT: vmovq %rax, %xmm3
-; X64-AVX2-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-AVX2-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
-; X64-AVX2-NEXT: vpaddq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpsllq $32, %xmm1, %xmm1
-; X64-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm0
+; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255]
+; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
+; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
+; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v2i64_neg_0_1:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: movq $-1, %rax
-; X64-AVX512DQ-NEXT: vmovq %rax, %xmm1
-; X64-AVX512DQ-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; X64-AVX512DQ-NEXT: vpmullq %xmm1, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmullq {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 0, i64 -1>
ret <2 x i64> %1
@@ -1674,48 +1648,40 @@ define <2 x i64> @mul_v2i64_15_neg_63(<2 x i64> %a0) nounwind {
;
; X64-LABEL: mul_v2i64_15_neg_63:
; X64: # %bb.0:
-; X64-NEXT: movdqa %xmm0, %xmm1
-; X64-NEXT: psrlq $32, %xmm1
-; X64-NEXT: movdqa {{.*#+}} xmm2 = [15,18446744073709551553]
-; X64-NEXT: pmuludq %xmm2, %xmm1
-; X64-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-NEXT: movq %rax, %xmm3
-; X64-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-NEXT: pmuludq %xmm0, %xmm3
-; X64-NEXT: paddq %xmm1, %xmm3
-; X64-NEXT: psllq $32, %xmm3
-; X64-NEXT: pmuludq %xmm2, %xmm0
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [15,18446744073709551553]
+; X64-NEXT: movdqa %xmm0, %xmm2
+; X64-NEXT: pmuludq %xmm1, %xmm2
+; X64-NEXT: movdqa %xmm0, %xmm3
+; X64-NEXT: psrlq $32, %xmm3
+; X64-NEXT: pmuludq %xmm1, %xmm3
+; X64-NEXT: pmuludq {{.*}}(%rip), %xmm0
; X64-NEXT: paddq %xmm3, %xmm0
+; X64-NEXT: psllq $32, %xmm0
+; X64-NEXT: paddq %xmm2, %xmm0
; X64-NEXT: retq
;
; X64-XOP-LABEL: mul_v2i64_15_neg_63:
; X64-XOP: # %bb.0:
-; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm1
-; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [15,18446744073709551553]
-; X64-XOP-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
-; X64-XOP-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-XOP-NEXT: vmovq %rax, %xmm3
-; X64-XOP-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-XOP-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
-; X64-XOP-NEXT: vpaddq %xmm1, %xmm3, %xmm1
-; X64-XOP-NEXT: vpsllq $32, %xmm1, %xmm1
-; X64-XOP-NEXT: vpmuludq %xmm2, %xmm0, %xmm0
+; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [15,18446744073709551553]
+; X64-XOP-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
+; X64-XOP-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X64-XOP-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
+; X64-XOP-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
; X64-XOP-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; X64-XOP-NEXT: vpsllq $32, %xmm0, %xmm0
+; X64-XOP-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; X64-XOP-NEXT: retq
;
; X64-AVX2-LABEL: mul_v2i64_15_neg_63:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm1
-; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [15,18446744073709551553]
-; X64-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
-; X64-AVX2-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; X64-AVX2-NEXT: vmovq %rax, %xmm3
-; X64-AVX2-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7]
-; X64-AVX2-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
-; X64-AVX2-NEXT: vpaddq %xmm1, %xmm3, %xmm1
-; X64-AVX2-NEXT: vpsllq $32, %xmm1, %xmm1
-; X64-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm0
+; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,18446744073709551553]
+; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
+; X64-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X64-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
+; X64-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; X64-AVX2-NEXT: retq
;
; X64-AVX512DQ-LABEL: mul_v2i64_15_neg_63:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
index c8136f4a18e7..d92db2e15c58 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
@@ -3505,7 +3505,7 @@ define <16 x i16> @shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_2
; AVX2-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
; AVX2-NEXT: retq
@@ -3529,7 +3529,7 @@ define <16 x i16> @shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_2
; XOPAVX2-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; XOPAVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
; XOPAVX2-NEXT: retq
@@ -5077,7 +5077,7 @@ define <16 x i16> @shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_3
; AVX2-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,8,9,2,3,10,11,4,5,12,13,6,7,14,15,16,17,24,25,18,19,26,27,20,21,28,29,22,23,30,31]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; AVX2-NEXT: retq
@@ -5102,7 +5102,7 @@ define <16 x i16> @shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_3
; XOPAVX2-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,8,9,2,3,10,11,4,5,12,13,6,7,14,15,16,17,24,25,18,19,26,27,20,21,28,29,22,23,30,31]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; XOPAVX2-NEXT: retq
@@ -5175,7 +5175,7 @@ define <16 x i16> @shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_2
; AVX2-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,0,1,10,11,2,3,12,13,4,5,14,15,6,7,24,25,16,17,26,27,18,19,28,29,20,21,30,31,22,23]
; AVX2-NEXT: retq
@@ -5200,7 +5200,7 @@ define <16 x i16> @shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_2
; XOPAVX2-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; XOPAVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,0,1,10,11,2,3,12,13,4,5,14,15,6,7,24,25,16,17,26,27,18,19,28,29,20,21,30,31,22,23]
; XOPAVX2-NEXT: retq
@@ -5516,7 +5516,7 @@ define <16 x i16> @shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_3
; AVX2-SLOW-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-SLOW-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; AVX2-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
@@ -5525,7 +5525,7 @@ define <16 x i16> @shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_3
; AVX2-FAST-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-FAST-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,2,3,6,7,8,9,12,13,10,11,14,15,16,17,20,21,18,19,22,23,24,25,28,29,26,27,30,31]
; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; AVX2-FAST-NEXT: retq
@@ -5550,7 +5550,7 @@ define <16 x i16> @shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_3
; XOPAVX2-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; XOPAVX2-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
@@ -5812,9 +5812,9 @@ define <16 x i16> @shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_1
;
; AVX2-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
+; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7,16,17,18,19,20,21,26,27,24,25,26,27,28,29,22,23]
; AVX2-NEXT: retq
;
@@ -5837,9 +5837,9 @@ define <16 x i16> @shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_1
;
; XOPAVX2-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
+; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15]
; XOPAVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7,16,17,18,19,20,21,26,27,24,25,26,27,28,29,22,23]
; XOPAVX2-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 21, i32 20, i32 21, i32 22, i32 11, i32 8, i32 9, i32 10, i32 29, i32 28, i32 29, i32 30, i32 11>
@@ -6012,9 +6012,9 @@ define <16 x i16> @shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_1
;
; AVX2-LABEL: shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_12:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm1[5,6,7],ymm0[8,9,10,11,12],ymm1[13,14,15]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6,7,8,9,10,11],ymm1[12],ymm0[13,14,15]
+; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3,4],ymm1[5,6,7],ymm0[8,9,10,11,12],ymm1[13,14,15]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7,8,9,10,11],ymm0[12],ymm1[13,14,15]
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
; AVX2-NEXT: retq
;
@@ -6036,9 +6036,9 @@ define <16 x i16> @shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_1
;
; XOPAVX2-LABEL: shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_12:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm1[5,6,7],ymm0[8,9,10,11,12],ymm1[13,14,15]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6,7,8,9,10,11],ymm1[12],ymm0[13,14,15]
+; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3,4],ymm1[5,6,7],ymm0[8,9,10,11,12],ymm1[13,14,15]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7,8,9,10,11],ymm0[12],ymm1[13,14,15]
; XOPAVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
; XOPAVX2-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 21, i32 22, i32 23, i32 0, i32 1, i32 2, i32 3, i32 12, i32 29, i32 30, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12>
@@ -6194,9 +6194,9 @@ define <16 x i16> @shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_1
;
; AVX2-LABEL: shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_10:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3,4,5,6,7],ymm0[8,9,10],ymm1[11,12,13,14,15]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15]
+; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3,4,5,6,7],ymm0[8,9,10],ymm1[11,12,13,14,15]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7,8,9],ymm0[10],ymm1[11,12,13,14,15]
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20,21]
; AVX2-NEXT: retq
;
@@ -6219,9 +6219,9 @@ define <16 x i16> @shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_1
;
; XOPAVX2-LABEL: shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_10:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3,4,5,6,7],ymm0[8,9,10],ymm1[11,12,13,14,15]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
-; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15]
+; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3,4,5,6,7],ymm0[8,9,10],ymm1[11,12,13,14,15]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
+; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7,8,9],ymm0[10],ymm1[11,12,13,14,15]
; XOPAVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20,21]
; XOPAVX2-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 1, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31, i32 8, i32 9, i32 10>
@@ -6378,7 +6378,7 @@ define <16 x i16> @shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_2
; AVX2-LABEL: shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_26:
; AVX2: # %bb.0:
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15]
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20,21]
; AVX2-NEXT: retq
@@ -6402,7 +6402,7 @@ define <16 x i16> @shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_2
; XOPAVX2-LABEL: shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_26:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15]
; XOPAVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20,21]
; XOPAVX2-NEXT: retq
@@ -6456,7 +6456,7 @@ define <16 x i16> @shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_2
; AVX2-LABEL: shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_28:
; AVX2: # %bb.0:
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5,6,7],ymm1[8,9,10,11,12],ymm0[13,14,15]
-; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6,7,8,9,10,11],ymm1[12],ymm0[13,14,15]
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
; AVX2-NEXT: retq
@@ -6481,7 +6481,7 @@ define <16 x i16> @shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_2
; XOPAVX2-LABEL: shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_28:
; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5,6,7],ymm1[8,9,10,11,12],ymm0[13,14,15]
-; XOPAVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
+; XOPAVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[2,3]
; XOPAVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6,7,8,9,10,11],ymm1[12],ymm0[13,14,15]
; XOPAVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
; XOPAVX2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
index be6ece76420c..94b00fbd937e 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
@@ -46,8 +46,7 @@ define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) {
; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512F-NEXT: movq $-1, %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
+; AVX512F-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
diff --git a/llvm/test/CodeGen/X86/vector-trunc-math.ll b/llvm/test/CodeGen/X86/vector-trunc-math.ll
index 18463a993c90..38cd2a3ae968 100644
--- a/llvm/test/CodeGen/X86/vector-trunc-math.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc-math.ll
@@ -2352,11 +2352,8 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) {
define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v4i64_v4i32:
; SSE: # %bb.0:
-; SSE-NEXT: movl $1, %eax
-; SSE-NEXT: movq %rax, %xmm2
-; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
-; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: retq
;
@@ -2508,10 +2505,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v16i64_v16i8:
; SSE: # %bb.0:
-; SSE-NEXT: movl $1, %eax
-; SSE-NEXT: movq %rax, %xmm8
-; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7]
-; SSE-NEXT: pmuludq %xmm8, %xmm0
+; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm2
; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm3
@@ -2539,10 +2533,7 @@ define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
;
; AVX1-LABEL: trunc_mul_const_v16i64_v16i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: movl $1, %eax
-; AVX1-NEXT: vmovq %rax, %xmm4
-; AVX1-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
-; AVX1-NEXT: vpmuludq %xmm4, %xmm0, %xmm8
+; AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm8
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm5
diff --git a/llvm/test/CodeGen/X86/vector-trunc.ll b/llvm/test/CodeGen/X86/vector-trunc.ll
index 9a1199f1ac59..36f7d46cd332 100644
--- a/llvm/test/CodeGen/X86/vector-trunc.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc.ll
@@ -1842,7 +1842,8 @@ define <8 x i16> @PR32160(<8 x i32> %x) {
;
; AVX2-SLOW-LABEL: PR32160:
; AVX2-SLOW: # %bb.0:
-; AVX2-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
+; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,2,2,3,4,5,6,7]
; AVX2-SLOW-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: retq
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